Results 51 to 60 of about 2,650,279 (206)
Efficient Object Detection Framework and Hardware Architecture for Remote Sensing Images
Remote Sensing, 2019 Object detection in remote sensing images on a satellite or aircraft has important economic and military significance and is full of challenges. This task requires not only accurate and efficient algorithms, but also high-performance and low power ...
Lin Li, Shengbing Zhang, Juan Wu
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Cascade: hardware for high/variable precision arithmetic [PDF]
, 1989 technical reportThe Cascade hardware architecture for high/variable precision arithmetic is described. It uses a radix-16 redundant signed-digit number representation and directly supports single or multiple precision addition, subtraction ...
Cascade hardware; Precision arithmetic +1 more
core
Low-Complexity Hardware Architecture of APN Permutations Using TU-Decomposition [PDF]
Functions with good cryptographic properties which are used as S-boxes in the design of block ciphers have a fundamental importance to the security of these ciphers since they determine the resistance to various kinds of cryptanalytic attacks.
Imaña, José L. +4 more
core +1 more source
EURASIP Journal on Advances in Signal Processing, 2006 This paper presents an architecture that combines VLIW (very long instruction word) processing with the capability to introduce application-specific customized instructions and highly parallel combinational hardware functions for the acceleration of ...
Hoare Raymond R +6 more
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The architecture of the new NLDBM hardware.
, 2020 The architecture of the new NLDBM hardware.
Akshay Parnami (8525448) +5 more
core +1 more source
CLEI Electronic Journal, 2010 This work presents a dedicated hardware design for the Forward Quantization Module (Q module) of the H.264/AVC Video Coding Standard, using optimized multipliers.
Felipe Sampaio +3 more
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An FPGA-Based Architecture for the Versatile Video Coding Multiple Transform Selection Core
IEEE Access, 2020 Versatile video coding (VVC) will be released by 2020, and it is expected to be the nextgeneration video coding standard. One of its enhancements is multiple transform selection (MTS) for core transform. MTS uses three different types of 2D discrete sine/
Matias J. Garrido +5 more
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Efficient cross-architecture hardware virtualisation [PDF]
, 2017 Hardware virtualisation is the provision of an isolated virtual environment that represents real physical hardware. It enables operating systems, or other system-level software (the guest), to run unmodified in a “container” (the virtual machine) that
Spink, Thomas
core
Highly-Efficient Hardware Architecture for ML-KEM PQC Standard
IEEE Open Journal of Circuits and SystemsThe advent of quantum computers, with their immense computational potential, poses significant threats to traditional cryptographic systems. In response, NIST announced the quantum-resistant Module Lattice-based Key Encapsulation Mechanism (ML-KEM ...
Haesung Jung +2 more
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Hardware Architecture Design for WSN Runtime Extension
International Journal of Distributed Sensor Networks, 2013 Internet of Things imposes demanding requirements on wireless sensor networks as key players in context awareness procurement. Temporal and spatial ubiquities are one of the essential features that meet technology boundaries in terms of energy management.
Ángel Asensio +3 more
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