Results 121 to 130 of about 717,844 (304)
This paper presents a novel hardware-software co-design approach to accelerate Q-learning algorithms using a RISC-V-based System-on-Chip (SoC) design.
Yahwista Salomo +3 more
doaj +1 more source
A Heterogeneous Hardware Accelerator for Image Classification in Embedded Systems. [PDF]
Pérez I, Figueroa M.
europepmc +1 more source
A Variable-Size FFT Hardware Accelerator Based on Matrix Transposition
Fast Fourier transform (FFT) is the kernel and the most time-consuming algorithm in the domain of digital signal processing, and the FFT sizes of different applications are very different.
Chen, Xiaowen, +3 more
core +1 more source
Helicity‐Defined Analog Conductance States in Chiral Perovskite Synapses
Chiral perovskite synapses convert the handedness of circularly polarized light into persistent analog memory during electrical programming. An optimized n = 3 structure combines strong helicity selectivity with low read noise, enabling 72 distinct conductance levels.
Min Jong Lee +16 more
wiley +1 more source
Development of a novel method for synthesizing Ni single atom catalysts for highly selective electrochemical CO2 reduction in situ. This catalyst achieves 100% selectivity for CO and is formed in an industrially relevant cell architecture. Using post‐mortem XRD, STEM, and EDS and operando XAS, the identity of the active site and the mechanism behind ...
Ian Street +5 more
wiley +1 more source
iDocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing. [PDF]
Tekleyohannes MK +5 more
europepmc +1 more source
The Hardware Accelerator SFDL/SCL.
This paper presents a new multiprocessor architecture for modelling and simulation of digital circuits. To speed up the simulation process a special static algorithm for dividing modelled circuit components into equivalent classes (before the simulation starts) has been designed. In components of one class events will never appear at the same time. The
Blatný, J., Bartoněk, D.
openaire +2 more sources
Breaking Bottlenecks in Solid Electrolyte Discovery With Large Artificial Intelligence Models
Large AI models are presented as a route to break key bottlenecks in solid electrolyte discovery by linking materials databases, machine‐learning interatomic potentials, large language models, and autonomous experiments. This perspective highlights how AI can accelerate the identification of solid electrolytes with fast ion transport, stable interfaces,
Eric Jianfeng Cheng +24 more
wiley +1 more source
NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark. [PDF]
Lu A, Peng X, Li W, Jiang H, Yu S.
europepmc +1 more source
A DIAMOND CO2 LASER-DRIVEN TEST ACCELERATOR
[[abstract]]This goal of this project is to demonstrate electron acceleration in a laser-driven accelerator structure in a vacuum. The proposed accelerator is driven by the pulsed CO2 laser and the 75 MeV electron beam at the Accelerator Test Facility ...
Y.C. Huang;A.C. Chiang;Y.Y. Lin
core

