Results 61 to 70 of about 1,050,120 (328)
CRYPHTOR: A Memory-Unified NTT-Based Hardware Accelerator for Post-Quantum CRYSTALS Algorithms
IEEE AccessThis paper presents the design and FPGA implementation of a hardware accelerator for the Post-Quantum CRYSTALS-Kyber and CRYSTALS-Dilithium algorithms, named CRYPHTOR (CRYstals Polynomial HW acceleraTOR).
S. Matteo, Ivan Sarno, Sergio Saponara
semanticscholar +1 more source
Hardware Acceleration of Sparse Support Vector Machines for Edge Computing
Elektronika ir Elektrotechnika, 2020 In this paper, a hardware accelerator for sparse support vector machines (SVM) is proposed. We believe that the proposed accelerator is the first accelerator of this kind.
Vuk Vranjkovic, Rastislav Struharik
doaj +1 more source
Accelerating Fully Homomorphic Encryption in Hardware
IEEE Transactions on Computers, 2014 We present a custom architecture for realizing the Gentry-Halevi fully homomorphic encryption (FHE) scheme. This contribution presents the first full realization of FHE in hardware. The architecture features an optimized multi-million bit multiplier based on the Schonhage Strassen multiplication algorithm.
Doroez, Yarkin +2 more
openaire +3 more sources
The Jefferson Lab 12 GeV Upgrade
, 2010 Construction of the 12 GeV upgrade to the Continuous Electron Beam Accelerator Facility (CEBAF) at the Thomas Jefferson National Accelerator Facility is presently underway.
McKeown, R. D.
core +2 more sources
Energy efficient packet classification hardware accelerator [PDF]
, 2008 Packet classification is an important function in a router's line-card. Although many excellent solutions have been proposed in the past, implementing high speed packet classification reaching up to OC-192 and even OC-768 with reduced cost and low power ...
Kennedy, Alan, Liu, Bin, Wang, Xiaojun
core +1 more source
Hardware Accelerated Power Estimation [PDF]
Design, Automation and Test in Europe, 2005 In this paper, we present power emulation, a novel design paradigm that utilizes hardware acceleration for the purpose of fast power estimation. Power emulation is based on the observation that the functions necessary for power estimation (power model evaluation, aggregation, etc.) can be implemented as hardware circuits.
Coburn, Joel +2 more
openaire +3 more sources
A High-Throughput Hardware Accelerator for Network Entropy Estimation Using Sketches
IEEE Access, 2021 Network traffic monitoring uses empirical entropy to detect anomalous events such as various types of attacks. However, the exact computation of the entropy in high-speed networks is a difficult process due to the limited memory resources available in ...
Javier E. Soto +4 more
semanticscholar +1 more source
Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification
, 2018 Modern Systems-on-Chip (SoC) designs are increasingly heterogeneous and contain specialized semi-programmable accelerators in addition to programmable processors.
Gupta, Aarti +5 more
core +1 more source
Audio Denoising Coprocessor Based on RISC-V Custom Instruction Set Extension
Acoustics, 2022 As a typical active noise control algorithm, Filtered-x Least Mean Square (FxLMS) is widely used in the field of audio denoising. In this study, an audio denoising coprocessor based on Retrenched Injunction System Computer-V (RISC-V), a custom ...
Jun Yuan +5 more
doaj +1 more source
Neural Architecture Search and Hardware Accelerator Co-Search: A Survey
IEEE Access, 2021 Deep neural networks (DNN) are now dominating in the most challenging applications of machine learning. As DNNs can have complex architectures with millions of trainable parameters (the so-called weights), their design and training are difficult even for
L. Sekanina
semanticscholar +1 more source