Results 71 to 80 of about 1,050,120 (328)

Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators

, 2020
We show that DNN accelerator micro-architectures and their program mappings represent specific choices of loop order and hardware parallelism for computing the seven nested loops of DNNs, which enables us to create a formal taxonomy of all existing dense
Bell, Steven Emberton, Cao, Kaidi, Gao, Mingyu, Ha, Heonjae, Horowitz, Mark, Kozyrakis, Christos, Liu, Qiaoyi, Nayak, Ankita, Pu, Jing, Raina, Priyanka, Setter, Jeff Ou, Yang, Xuan   +11 more
core   +1 more source

Hydra: An Accelerator for Real-Time Edge-Aware Permeability Filtering in 65nm CMOS

, 2017
Many modern video processing pipelines rely on edge-aware (EA) filtering methods. However, recent high-quality methods are challenging to run in real-time on embedded hardware due to their computational load. To this end, we propose an area-efficient and
Benini, Luca, Cavigelli, Lukas, Eggimann, Manuel, Gloor, Christelle, Schaffner, Michael, Scheidegger, Florian, Smolic, Aljosa   +6 more
core   +1 more source

Rethinking plastic waste: innovations in enzymatic breakdown of oil‐based polyesters and bioplastics

FEBS Open Bio, EarlyView.
Plastic pollution remains a critical environmental challenge, and current mechanical and chemical recycling methods are insufficient to achieve a fully circular economy. This review highlights recent breakthroughs in the enzymatic depolymerization of both oil‐derived polyesters and bioplastics, including high‐throughput protein engineering, de novo ...
Elena Rosini, Nicolò Antonelli, Gianluca Molla   +2 more
wiley   +1 more source

Design of exact reduct rough set hardware accelerator for early-stage diabetes risk prediction

Results in Control and Optimization
Diabetes is a prevalent, chronic metabolic disorder worldwide. Detecting and predicting risks early are vital for timely intervention. In this paper, the design and implementation of an Exact Reduct Rough Set Hardware Accelerator is presented for early ...
Kanchan S. Tiwari, Uma D. Dattasamje, Rekha S. Kadam, Manisha A. Dudhedia, Aishwarya A. Andhale, Jayshree R. Pansare, Bapurao G. Marlapalle   +6 more
doaj   +1 more source

An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization

International Journal of Reconfigurable Computing, 2013
Current software-based packet classification algorithms exhibit relatively poor performance, prompting many researchers to concentrate on novel frameworks and architectures that employ both hardware and software components. The Packet Classification with
O. Ahmed, S. Areibi, R. Collier, G. Grewal   +3 more
doaj   +1 more source

SPH Simulations with Reconfigurable Hardware Accelerator

, 2006
We present a novel approach to accelerate astrophysical hydrodynamical simulations. In astrophysical many-body simulations, GRAPE (GRAvity piPE) system has been widely used by many researchers.
Fukushige, T., Hamada, T., Nakasato, N.
core   +2 more sources

Ultra-high throughput string matching for deep packet inspection [PDF]

, 2010
Deep Packet Inspection (DPI) involves searching a packet's header and payload against thousands of rules to detect possible attacks. The increase in Internet usage and growing number of attacks which must be searched for has meant hardware acceleration ...
Kennedy, Alan, Liu, Bin, Liu, Zhen, Wang, Xiaojun   +3 more
core   +1 more source

Analysing the significance of small conformational changes and low occupancy states in serial crystallographic data

FEBS Open Bio, EarlyView.
This protocol paper outlines methods to establish the success of a time‐resolved serial crystallographic experiment, by means of statistical analysis of timepoint data in reciprocal space and models in real space. We show how to amplify the signal from excited states to visualise structural changes in successful experiments.
Jake Hill, Yelyzaveta Pulnova, Elke De Zitter, Helen M. Ginn, Briony A. Yorke   +4 more
wiley   +1 more source

Novel CNN Accelerator Design With Dual Benes Network Architecture

IEEE Access, 2023
We presented a novel hardware architecture that uses dual Benes networks to accelerate Convolutional Neural Network (CNN) algorithms. This architecture can reduce the need for high-speed buses and maintain a high-speed connection between execution units ...
Chun Yan Lo, Chiu-Wing Sham, Chong Fu
doaj   +1 more source

A Robust Adaptive One‐Sample‐Ahead Preview Super‐Twisting Sliding Mode Controller

International Journal of Adaptive Control and Signal Processing, EarlyView.
Block Diagram of the Robust Adaptive One‐Sample‐Ahead Preview Super‐Twisting Sliding Mode Controller. ABSTRACT This article introduces a discrete‐time robust adaptive one‐sample‐ahead preview super‐twisting sliding mode controller. A stability analysis of the controller by Lyapunov criteria is developed to demonstrate its robustness in handling both ...
Guilherme Vieira Hollweg, Paulo Jefferson Dias de Oliveira Evald, Shivam Chaturvedi, Hilton Abilio Gründling, Rodrigo Varella Tambara, Wencong Su   +5 more
wiley   +1 more source