Results 11 to 20 of about 3,717 (263)
Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey
IEEE Access, 2022 In the modern-day era of technology, a paradigm shift has been witnessed in the areas involving applications of Artificial Intelligence (AI), Machine Learning (ML), and Deep Learning (DL).
Pudi Dhilleswararao +3 more
doaj +1 more source
Sensors, 2022 Deep neural networks have been deployed in various hardware accelerators, such as graph process units (GPUs), field-program gate arrays (FPGAs), and application specific integrated circuit (ASIC) chips.
Liang Chang, Xin Zhao, Jun Zhou
doaj +1 more source
Hardware-accelerated dynamic binary translation [PDF]
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017 Dynamic Binary Translation (DBT) is often used in hardware/software co-design to take advantage of an architecture model while using binaries from another one. The co-development of the DBT engine and of the execution architecture leads to architecture with special support to these mechanisms.
Rokicki, Simon +2 more
openaire +2 more sources
Sensors, 2023 Though custom deep learning (DL) hardware accelerators are attractive for making inferences in edge computing devices, their design and implementation remain a challenge. Open-source frameworks exist for exploring DL hardware accelerators.
Dennis Agyemanh Nana Gookyi +4 more
doaj +1 more source
Convolutional Neural Networks using FPGA-based Pipelining
Iraqi Journal for Computer Science and Mathematics, 2023 In order to speed up convolutional neural networks (CNNs), this study gives a complete overview of the use of FPGA-based pipelining for hardware acceleration of CNNs.
Gheni A. Ali, ahmed hussein ali
doaj +1 more source
Resistive Neural Hardware Accelerators
Proceedings of the IEEE, 2023 Deep Neural Networks (DNNs), as a subset of Machine Learning (ML) techniques, entail that real-world data can be learned and that decisions can be made in real-time. However, their wide adoption is hindered by a number of software and hardware limitations. The existing general-purpose hardware platforms used to accelerate DNNs are facing new challenges
Kamilya Smagulova +4 more
openaire +3 more sources
Hardware Accelerators for Real-Time Face Recognition: A Survey
IEEE Access, 2022 Real-time face recognition has been of great interest in the last decade due to its wide and varied critical applications which include biometrics, security in public places, and identification in login systems.
Asma Baobaid +3 more
doaj +1 more source
MODEL OF AUTOMATED SYNTHESIS TOOL FOR HARDWARE ACCELERATORS OF CONVOLUTIONAL NEURAL NETWORKS FOR PROGRAMMABLE LOGIC DEVICES [PDF]
Научно-технический вестник информационных технологий, механики и оптики, 2020 Currently, more and more tasks on image processing and analysis are being solved using convolutional neural networks. Neural networks implemented using high-level programming languages, libraries and frameworks cannot be used in real-time systems, for ...
Victor A. Egiazarian +1 more
doaj +1 more source
Transactions on Cryptographic Hardware and Embedded Systems, 2020 This paper presents a set of efficient and parameterized hardware accelerators that target post-quantum lattice-based cryptographic schemes, including a versatile cSHAKE core, a binary-search CDT-based Gaussian sampler, and a pipelined NTT-based ...
Wen Wang +5 more
doaj +1 more source
Numerical behavior of NVIDIA tensor cores [PDF]
PeerJ Computer Science, 2021 We explore the floating-point arithmetic implemented in the NVIDIA tensor cores, which are hardware accelerators for mixed-precision matrix multiplication available on the Volta, Turing, and Ampere microarchitectures.
Massimiliano Fasi +3 more
doaj +2 more sources