Results 211 to 220 of about 3,717 (263)

Optimizing deep learning models for on-orbit deployment through neural architecture search. [PDF]

Sci Rep
Del Prete R, Thind PK, Mazzeo A, Whitley M, Papa L, Longépé N, Meoni G.   +6 more
europepmc   +1 more source

Exploring subthreshold processing for next-generation TinyAI. [PDF]

Front Comput Neurosci
Nakhle F, Harfouche AH, Karam H, Tserolas V.   +3 more
europepmc   +1 more source

Balancing accuracy and efficiency: co-design of hybrid quantization and unified computing architecture for spiking neural networks. [PDF]

Front Neurosci
Li J, Xu M, Dong H, Lan B, Liu Y, Chen H, Zhuang Y, Xie Y, Chen L.   +8 more
europepmc   +1 more source

Hardware-Oriented Approximations of Softmax and RMSNorm for Efficient Transformer Inference. [PDF]

Micromachines (Basel)
Kang Y, Wang D.
europepmc   +1 more source

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Hardware accelerators for CAD

Computer-Aided Engineering Journal, 1989
At Brunei University, a small research team has been developing special-purpose hardware and algorithms that will greatly reduce the run times of CAD tasks currently run on conventional von Neumann computers. This article gives an example to illustrate the benefits that can be obtained by the use of hardware accelerators, indicating also how these ...
exaly   +2 more sources

Hardware Accelerated Voxelisation

Computers & Graphics, 2000
Abstract This paper presents a hardware accelerated approach to the voxelization of a wide range of 3D objects, including curves/surfaces, solids, and volumetric CSG models. It allows 3D scenes to be modeled and manipulated in their own representations, and generates the volume representations of regions of interest on-the-fly for volumetric ...
Shiaofen Fang, Hongsheng Chen
openaire   +1 more source

Hardware Accelerated Data Analysis

Parallel Computing in Electrical Engineering, International Conference on, 2004
In this paper we present a massively parallel hardware accelerator for neural network based data mining applications. We use Self-Organizing Maps (SOM) for the analysis of very large datasets. One example is the analysis of semiconductor fabrication process data, which demands very high performance in order to achieve acceptable simulation times.
Franzmeier, M., Pohl, C., Porrmann, Mario, Rückert, Ulrich, ARRAY(0x919d200)   +4 more
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Multimedia Execution Hardware Accelerator

Journal of VLSI signal processing systems for signal, image and video technology, 2001
zbMATH Open Web Interface contents unavailable due to conflicting licenses.
Hakkennes, Edwin, Vassiliadis, Stamatis
openaire   +2 more sources

Hybrid binary-unary hardware accelerator

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
Stream-based computing such as stochastic computing has been used in recent years to create designs with significantly smaller area by harnessing unary encoding of data. However, the area saving comes at an exponential price in latency, making the area × delay cost unattractive.
S. Rasoul Faraji, Kia Bazargan
openaire   +1 more source