Results 221 to 230 of about 3,717 (263)
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IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology', 2003
A novel signal processing architecture is described that performs the fast Fourier transform (FFT) in near-optimum time, with minimal hardware. State-of-the-art circuitry and careful layout support ultrafast operations. The processor is capable of executing several signal processing algorithms utilizing a microprogrammable control unit.
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A novel signal processing architecture is described that performs the fast Fourier transform (FFT) in near-optimum time, with minimal hardware. State-of-the-art circuitry and careful layout support ultrafast operations. The processor is capable of executing several signal processing algorithms utilizing a microprogrammable control unit.
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2006 International Conference on Field Programmable Logic and Applications, 2006
Hard disk storage capacity has continued to rise whilst at the same time the cost per megabyte continues to fall. This, combined with increased usage of digital storage for documents, photography and video for both home and business use has led to increased need for reliable data storage system.
Michael Gilroy, James Irvine
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Hard disk storage capacity has continued to rise whilst at the same time the cost per megabyte continues to fall. This, combined with increased usage of digital storage for documents, photography and video for both home and business use has led to increased need for reliable data storage system.
Michael Gilroy, James Irvine
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Hardware accelerated multichannel receiver
2009 IEEE Aerospace conference, 2009Software-based radios implemented on general-purpose processors are cheaper, easier, and faster to develop, maintain, and upgrade than hardware-based equivalents. Unfortunately, today's general-purpose processors are not fast enough to process certain waveforms. The current alternative is to use application-specific integrated circuits (ASICs) or field-
Eric J. McDonald +2 more
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Hardware Accelerated Wavelet Transformations
2000Wavelets and related multiscale representations are important means for edge detection and processing as well as for segmentation and registration. Due to the computational complexity of these approaches no interactive visualization of the extraction process is possible nowadays.
Matthias Hopf, Thomas Ertl
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Domain-specific hardware accelerators
Communications of the ACM, 2020DSAs gain efficiency from specialization and performance from parallelism.
Dally, William +2 more
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Hardware accelerated application integration
Proceedings of the Second International Workshop on Active Middleware on Modern Hardware, 2017In this talk we set the emerging domain of application integration into the context of recent hardware advances.
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ACM Transactions on Embedded Computing Systems, 2011
Inexpensive, reliable hard disk storage is increasingly required in both businesses and the home. As disk capacities increase and multiple drives are combined in one system the probability of multiple disk failures increases. Through the adoption of RAID 6 the capability to recover from up to two simultaneous disk failures becomes available.
Gilroy, Michael +2 more
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Inexpensive, reliable hard disk storage is increasingly required in both businesses and the home. As disk capacities increase and multiple drives are combined in one system the probability of multiple disk failures increases. Through the adoption of RAID 6 the capability to recover from up to two simultaneous disk failures becomes available.
Gilroy, Michael +2 more
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Hardware Accelerator for BLAST
2012 IEEE 6th International Symposium on Embedded Multicore SoCs, 2012The basic local alignment search tool (BLAST) is one of the most popular sequence alignment tools available. Sequence alignment is used to extract similar parts of an input protein (or DNA) sequence from protein (or DNA) databases, in order to investigate biological evolution and genomic genealogy.
Shizuka Ishikawa +2 more
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Disparity Map Hardware Accelerator
2008 International Conference on Reconfigurable Computing and FPGAs, 2008Hardwired acceleration units capable of exploiting the parallelism of images rely on highly customized memory organizations. In this paper we analyze a widely used depth-discontinuity-algorithm applied in stereo vision systems. The main processing kernels are decomposed, and a hardwired acceleration unit is proposed for speeding up the computation. The
Humberto Calderón +2 more
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Hardware accelerated FPGA placement
Microelectronics Journal, 2009A key advantage of field-programmable gate arrays (FPGAs) over full-custom and semi-custom devices is that they provide relatively quick implementation from concept to physical realization. However, as modern FPGAs reach close to one million logic blocks, more efficient and scalable FPGA placement algorithms are needed.
Christian Fobel +2 more
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