Results 81 to 90 of about 2,650,279 (206)

An SHA-3 Hardware Architecture against Failures Based on Hamming Codes and Triple Modular Redundancy. [PDF]

Sensors (Basel), 2022
Torres-Alvarado A, Morales-Rosales LA, Algredo-Badillo I, López-Huerta F, Lobato-Báez M, López-Pimentel JC.   +5 more
europepmc   +1 more source

A hardware/software co-design architecture of canny edge detection

, 2012
The Canny edge detection algorithm has been widely used in image processing and computer vision applications. This algorithm is complex since it requires successive computationally-heavy stages such as smoothing, computing gradient, thinning and ...
Ullah Sheikh, Usman, Sheikh, Usman Ullah, Marsono, Muhammad Nadzir, Muhammad Nadzir Marsono, Haghi, Abbas, Usman Ullah Sheikh, Abbas Haghi   +6 more
core   +1 more source

Photonic-digital hybrid artificial intelligence hardware architectures: at the interface of the real and virtual worlds

JPhys Photonics
Artificial intelligence (AI) technology has become an undeniable presence in society, as seen in the growing use of chatbots (e.g. ChatGPT) and recent Nobel Prize awards.
Lília M S Dias, Dinis O Abranches, Ana R Bastos, Lianshe Fu, Albano N Carneiro Neto, Rui F P Pereira, Verónica de Zea Bermudez, Elias Towe, Rute A S Ferreira, Paulo S B André   +9 more
doaj   +1 more source

An efficient hardware architecture based on an ensemble of deep learning models for COVID -19 prediction. [PDF]

Sustain Cities Soc, 2022
R S, Thaseen IS, M V, M D, M A, R M, Mahendran A, Alnumay W, Chatterjee P.   +8 more
europepmc   +1 more source

Fine grain algorithm parallelization on a hybrid control-flow and dataflow processor

Journal of Big Data
The execution time of a high-performance computing algorithm is influenced by various factors, including the algorithm's scalability, the selected hardware for processing elements, and the communication speed between these elements. This study utilizes a
Nenad Korolija
doaj   +1 more source

Hardware architecture for adaptive filtering based on energy-CFAR processor for radar target detection

, 2010
A hardware architecture that implements an adaptive filter based on energy analysis of radar echoes to improve the detection of the Constant False Alarm Rate (CFAR) algorithm is presented. Signal processing based on energy analysis emphasizes the edge of
SANTOS MARTIN LOPEZ ESTRADA, RENE ARMANDO CUMPLIDO PARRA   +1 more
core  

A self-adaptive hardware architecture with fault tolerance capabilities

, 2013
This paper describes a Fault Tolerance System (FTS) implemented in a new self-adaptive hardware architecture. This architecture is based on an array of cells that implements in a distributed way self-adaptive capabilities.
Moreno Aróstegui, Juan Manuel, Soto, Javier, Cabestany Moncusí, Joan   +2 more
core   +1 more source

Orchestration mechanism for VNF hardware acceleration resources in SDN/NFV architecture

Tongxin xuebao, 2018
The hardware acceleration mechanism for VNF (virtual network function) is recently a hot research topic in SDN/NFV architecture because of the low processing performance of VNF.Once hardware acceleration resources have been plugged into the network,how ...
Tong DUAN, Julong LAN, Yuxiang HU, Hongwei FAN   +3 more
doaj   +2 more sources

PC-Grade Parallel Processing and Hardware Acceleration for Large-Scale Data Analysis [PDF]

Arguably, modern graphics processing units (GPU) are the first commodity, and desktop parallel processor. Although GPU programming was originated from the interactive rendering in graphical applications such as computer games, researchers in the field ...
Yang, Su
core   +3 more sources

Real-Time Lossless Compression System for Bayer Pattern Images with a Modified JPEG-LS

Mathematics
Real-time lossless image compression based on the JPEG-LS algorithm is in high demand for critical missions such as satellite remote sensing and space exploration due to its excellent balance between complexity and compression rate.
Xufeng Li, Li Zhou, Yan Zhu
doaj   +1 more source