Results 21 to 30 of about 495,121 (361)
PGPG: An Automatic Generator of Pipeline Design for Programmable GRAPE Systems [PDF]
We have developed PGPG (Pipeline Generator for Programmable GRAPE), a software which generates the low-level design of the pipeline processor and communication software for FPGA-based computing engines (FBCEs).
Fukushige, Toshiyuki+2 more
core +2 more sources
Real-Time Digital Simulation (RTDS) is a powerful tool in modeling and analyzing electrical and drive systems because it provides an efficient and accurate process. There are several hardware devices for this type of simulation; however, their high costs
Janailson Queiroz+4 more
doaj +1 more source
FPGA-Based Single-Phase PV Inverter Using Unipolar and Bipolar SPWM Control Techniques [PDF]
The study presents circuitry modeling and methodology to integrate solar photovoltaic (PV) energy with grid (AC) sources to supplement household appliances during a power cut-off or restricted supply period and alternating charge deep cycle batteries ...
Murtadha Sadeq, Hanan A. Akkar
doaj +1 more source
ANALYSIS OF TOOLS AND TECHNOLOGIES OF FaaS DEVELOPMENT
This article has analyzed the most effective integrated development environments from leading programmable logical device (PLD) manufacturers. Heterogeneous calculations and the applicability of a general approach to the description of hardware ...
Инна Николаевна Заризенко+1 more
doaj +1 more source
Cryptographic Algorithm Based on Hybrid One-Dimensional Cellular Automata
The theory and application of cellular automata (CA) for a stream cipher-based encryption principle are presented in this study. Certain fundamental transformations are developed based on CA theory regarding decentralized computation for modeling ...
George Cosmin Stănică+1 more
doaj +1 more source
Meta-functional languages for hardware design and verification [PDF]
The approach of embedding hardware description languages in general-purpose languages has been widely explored in the literature and has been shown to aid hardware design and verification.
Pace, Gordon J.+2 more
core +1 more source
Design and implementation of partial dynamically reconfigurable FPGA process scheduling
In view of the diverse edge computing requirements of the 6G era, reconfigurable technology based on FPGAs can achieve lower latency and provide diversified services.
Qian Hongwen+5 more
doaj +1 more source
SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips [PDF]
This paper presents SIRENA, a CAD environment for the simulation and modelling of mixed-signal VLSI parallel processing chips based on cellular neural networks.
Carmona Galán, Ricardo+5 more
core +1 more source
Modified Welch Berlekamp Algorithm to Decode Reed Solomon Codes
In this paper, the Reed Solomon Code is decoded using the Welch-Berlekamp Algorithm. The RS Decoder is implemented using Hardware Description Language VHDL (VHSIC hardware Description Language) and simulated on Modelsim software.
Mahmudi Ali, Achmadi Sentot, Michael
doaj +1 more source
High Throughput Implementation of the Keccak Hash Function Using the Nios-II Processor
Presently, cryptographic hash functions play a critical role in many applications, such as digital signature systems, security communications, protocols, and network security infrastructures.
Argyrios Sideris+2 more
doaj +1 more source