Results 41 to 50 of about 20,240 (210)

Optimization of the symmetric encryption mode ECB dedicated to securing medical data [PDF]

Journal of Electrical and Electronics Engineering, 2021
Data security is a recurring problem to protected the private life of users, Data encryption is necessary but also delicate step to ensure at the same time speed and security of transmission and reception data, there are different models of cryptography ...
SEGHIRI Naouel, BABA-AHMED Mohammed Zakarya, BENMAMMAR Badr   +2 more
doaj  

Generation of Synthesizable Verilog Code From Natural Language Specifications

IEEE Access
This study presents a method for generating synthesizable Verilog code for digital integrated circuits directly from natural-language specifications. The approach combines large language models with parameter-efficient fine-tuning (specifically, Low-Rank
Daniil S. Yashchenko, Aleksandr Y. Romanov, Artur A. Ziazetdinov, Dmitry V. Telpukhov, Roman A. Solovyev   +4 more
doaj   +1 more source

Hardware accelerators for processing clusters in binary vectors [PDF]

ITM Web of Conferences
The paper suggests fast hardware accelerators for discovering clusters of zeros and/or ones in binary vectors. Any cluster is composed of successive bits with the same value (either 1 or 0). Search for such segments is required in many practical problems,
Skliarova Iouliia, Skliarov Valeri
doaj   +1 more source

LLHD: a multi-level intermediate representation for hardware description languages [PDF]

, 2020
Fabian Schuiki, Andreas Kurth, Tobias Grosser, Luca Benini   +3 more
openalex   +2 more sources

Opportunities and Challenges for Circuit Board Level Hardware Description Languages [PDF]

, 2020
Richard J. Lin, Björn Hartmann
openalex   +1 more source

Implementation of Loop Pipelining and Assignment Inlining in the C-to-HDL Translator

Труды Института системного программирования РАН, 2018
Implementing algorithms for field-programmable gate arrays using a hardware description language is a complex task. Therefore, it would be useful to have a tool that can efficiently translate an algorithm from a high-level language to a hardware ...
Alexey Merkulov, Andrey Belevantsev
doaj  

Space Vector Pulse Width Modulation for High-Speed Induction Motor Implemented in Nios II Softcore Processor

Power Electronics and Drives, 2018
The purpose of the article was to present the idea of space vector pulse width modulation (SVPWM) and implementation in Nios II softcore processor.
Chojowski Maciej
doaj   +1 more source

Design and implementation of two-dimensional digital finite impulse response filter using very high speed integrated circuit hardware description language

, 2022
Thingujam Churchil Singh, Manoj Kumar
openalex   +2 more sources

Architectural specification, exploration and simulation through rewriting-logic

Revista Colombiana de Computación, 2002
In recent years Arvind’s Group at MIT has shown the usefulness of term rewriting theory for the specification of processor architectures. In their approach processors specified by term rewriting systems are translated into a standard hardware description
Mauricio Ayala Rincón, Reiner W. Hartenstein, Rinaldi Maya Neto, Ricardo P. Jacobi, Carlos Humberto Llanos   +4 more
doaj  

Contribution to Synchronization and Tracking Modelisation in a CDMA Receiver

Journal of Engineering, 2013
We propose and analyze a noncoherent receiver with PN code tracking for direct sequence code division multiple access (DS-CDMA) communication systems. We employ the delay-lock loop (DLL) architectures for the tracking stage.
Aicha Alami Hassani, Mohcine Zouak, Mostafa Mrabti   +2 more
doaj   +1 more source