Results 51 to 60 of about 20,240 (210)

LabVIEW FPGA Implementation Of a PID Controller For D.C. Motor Speed Control [PDF]

Iraqi Journal for Electrical and Electronic Engineering, 2010
This Paper presents a novel hardware design methodology of digital control systems. For this, instead of synthesizing the control system using Very high speed integration circuit Hardware Description Language (VHDL), LabVIEW FPGA module from National
Fakhrulddin H. Ali , Mohammed Mahmood Hussein , Sinan M.B. Ismael   +2 more
doaj  

A design of codec based on HDMI2.0

Dianzi Jishu Yingyong, 2018
Based on the analysis of High-Definition Multimedia Interface(HDMI)2.0 specification, the circuit of codec was designed with the hardware description language, and the prototype verification was implemented on the FPGA platform.
Wei Guo
doaj   +1 more source

Design and HDL Implementation of Pulse-Arrival-Time Estimation Using XGBoost Regression With Tree-Recycling Architecture

IEEE Access
This paper presents a pulse-arrival-time (PAT) estimation scheme using Extreme Gradient Boosting (XGBoost) regression and its implementation with hardware description language (HDL).
Hyo-Jeong Choi, Ji-Yong Um
doaj   +1 more source

Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL

Algorithms, 2019
Intel recently introduced the Heterogeneous Architecture Research Platform, HARP. In this platform, the Central Processing Unit and a Field-Programmable Gate Array are connected through a high-bandwidth, low-latency interconnect and both share DRAM ...
Thomas Faict, Erik H. D’Hollander, Bart Goossens   +2 more
doaj   +1 more source

Calibration and Analysis of Source Code Similarity Measures for Verilog Hardware Description Language Projects [PDF]

, 2020
James F. Power, John Waldron
openalex   +1 more source

Design and Implementation of a Low Complexity Multiuser Detector for Hybrid CDMA Systems

Journal of Communications Software and Systems, 2005
In hybrid CDMA systems, multiuser detection (MUD) algorithms are adopted at the base station to reduce both multiple access and inter-symbol interference by exploitingspace-time (ST) signal processing techniques.
Vittorio Rampa
doaj  

Fine-grained hardware resource optimization and design for FPGA-based real-time simulation of large-scale renewable energy generations

International Journal of Electrical Power & Energy Systems
Real-time simulation of renewable energy generations (REGs) is essential for the development and testing of centralized scheduling controllers, inverter controllers and edge computing devices.
Yanfei Li, Zhiying Wang, Xiaopeng Fu, Peng Li, Ligang Zhao, Xiaoshan Wu   +5 more
doaj   +1 more source

Mixed-signal generator module:Design and Verification in MATLAB and Verilog hardware description language

, 2020
D Nguyen, S Kim, S Santhosh, V Hieu, A Don, M Africa, J Kim   +6 more
openalex   +1 more source

DESIGN AND IMPLEMENTATION OF FPGA-BASED FFT CO-PROCESSOR USING VERILOG HARDWARE DESCRIPTION LANGUAGE [PDF]

, 2021
Yung-Chong Lee, Yee Kit Chan, Voon Chet Koo   +2 more
openalex   +1 more source

Weaving Schematics and Code: Interactive Visual Editing for Hardware Description Languages [PDF]

, 2021
Richard J. Lin, Rohit Ramesh, Nikhil Jain, Josephine Koe, Ryan Nuqui, Prabal Dutta, Bjoern Hartmann   +6 more
openalex   +1 more source