Results 251 to 260 of about 4,696,608 (299)

Hardware implementation of a nonlinear processor

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349), 2003
Several advanced DSP algorithms, arising in applications such as wireless communications, computer graphics, computerized tomography, and speech compression, require extensive use of nonlinear functions. We discuss a new hardware approach to high-speed computation of nonlinear functions. With this approach all of the functions needed can be regularized
Vijay K. Jain, S. Shrivastava, A. D. Snider, D. Damerow, D. Chester   +4 more
openaire   +2 more sources

A HARDWARE IMPLEMENTATION OF THE APE100 ARCHITECTURE

International Journal of Modern Physics C, 1993
APE100 processors are based on a simple Single Instruction Multiple Data architecture optimized for the simulation of Lattice Field Theories or other complex physical systems. This paper describes the hardware implementation of the first APE100 machine.
BARTOLONI A, BASTIANELLO G, BATTISTA C, CABASINO S, MARZANO F, PAOLUCCI PS, PECH J, RAPUANO F, PANIZZI E, SARNO R, TODESCO GM, TORELLI M, TROSS W, VICINI P, CABIBBO N, FUCCI A, TRIPICCIONE, Raffaele   +16 more
openaire   +4 more sources

AES Embedded Hardware Implementation

Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007
The paper presents a parallel reconfigurable hardware implementation of the AES cryptographic algorithm developed for an embedded application. This new methodology directly maps a design described in a high level language, Handel-C, to FPGA platforms. The Handel-C approach narrows the gap between performance and flexibility, and thus, reduce the risk ...
Ould-cheikh Mourad, Si-Mohamed Lotfy, Noureddine Mehallegue, Ahmed Bouridane, Camel Tanougast   +4 more
openaire   +1 more source

Hardware implementation of a memory allocator

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools, 2003
It is generally felt that the complexity of system-on-chip (SOC) can only be addressed by intellectual-property (IP) based design. While IPs such as processor cores, memories, and bus controllers are being offered by many vendors, IP cores for dynamic memory management, an important task for any complex application, have been close to non-existent ...
Khushwinder Jasrotia, Jianwen Zhu
openaire   +1 more source

Hardware implementations of denormalized numbers

16th IEEE Symposium on Computer Arithmetic, 2003. Proceedings., 2004
Denormalized numbers are the most difficult type of numbers to implement in floating-point units. They are so complex that some designs have elected to handle them in software rather than hardware. This has resulted in execution times in the tens of thousands of cycles, which has made denormalized numbers useless to programmers.
Eric M. Schwarz, Martin S. Schmookler, Son Dao Trong   +2 more
openaire   +1 more source

Polar Decoding Hardware Implementation

2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2019
This paper presents hardware implementations of two principle polar decoding algorithms: Successive Cancellation Decoding (SCD) and Successive Cancellation List Decoding (SCL). The proposed designs are compliant with 3GPP specifications in terms of block length and frozen-set mapping.
Lam Vinh Qui Nguyen, Jean Dion, Nicolas Gresset   +2 more
openaire   +1 more source

Emission Analysis of Hardware Implementations

2014 17th Euromicro Conference on Digital System Design, 2014
Today, hardware implementations are the basis for many security applications, such as cryptographic ciphers. Such applications are realized using complex combinatorial logic circuits of substantial size. Therefore, understanding the gate-level implementation can be crucial for the attacker. However, Hardware Description Language (HDL) behavioral models
Shahin Tajik, Dmitry Nedospasov, Clemens Helfmeier, Jean-Pierre Seifert, Christian Boit   +4 more
openaire   +1 more source

Hardware Implementation of HS1-SIV

2017
Design of the hardware implementation of the CAESAR competition second round candidate, HS1-SIV, with regular cipher parameter settings is described in this paper. Given implementation of HS1-SIV cipher was developed in such a way to be conforming to the specification of the authenticated cipher as well as a hardware API.
Sergei Volokitin, Gerben Geltink
openaire   +2 more sources

A hardware implementation of the mechanism of multiprocessing

Microprocessors and Microsystems, 1999
Abstract The mechanism of multiprocessing (MMP) has been developed and implemented as an enhancement of a standard operating system (OS ES) to support efficient execution of fine-grained parallel activities. The MMP mechanism is presented through the description of its primitives, associated data structures and its interface with the OS ES.
Milo Tomasevic, Miroslav Bojovic, Jovan Djordjevic   +2 more
openaire   +2 more sources

A hardware implementation of realloc function

Integration, 1999
Abstract The memory intensive nature of object-oriented languages such as C++ and Java has created the need of a high-performance dynamic memory management. Object-oriented applications often generate higher memory intensity in the heap region. Thus, high-performance memory manager is needed to cope with such applications.
Witawas Srisa-an, Chia-Tien Dan Lo, J. Morris Chang   +2 more
openaire   +2 more sources