Results 251 to 260 of about 173,402 (304)

Implementing Exact Calculations in Hardware

IEEE Transactions on Computers, 1987
A technique for performing exact calculations is discussed. The technique uses single-modulus P arithmetic to perform calculations over the finite field of integers and the finite ring of integers. It is shown that the arithmetic operations modulo P (which obviously can be implemented in microprocessor configurations, VLSI, and/or software) can easily ...
Jay J. Thomas, Sydney R. Parker
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On the implementation of QIM FPGA hardware

2011 International Conference on Recent Trends in Information Systems, 2011
In this paper, we propose the FPGA implementation of a watermarking algorithm in the spatial domain. The paper put emphasis on Quantization Index Modulation based watermarking approach using dither sequences. The cost-effective data embedding algorithm can conceal watermark into original cover image coming from a sensor more rapidly than software ...
Abhishek Basu, Abhik Roy, Tirtha Shankar Das, Subir Kumar Sarkar   +3 more
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Hardware implementation

Proceedings of the December 9-11, 1968, fall joint computer conference, part II on - AFIPS '68 (Fall, part II), 1968
The area of hardware implementation shall be (some-what arbitrarily) defined to include placement, wire routing, terminal assignment, and the interface to hardware fabrication devices. At this stage, many companies have automated at least some of these steps.
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Hardware Implementation for a Genetic Algorithm

IEEE Transactions on Instrumentation and Measurement, 2008
A genetic algorithm (GA) can find an optimal solution in many complex problems. GAs have been widely used in many applications. A flexible-very-large-scale integration intellectual property for the GA has been proposed in this paper. This algorithm can dynamically perform various population sizes, fitness lengths, individual lengths, fitness functions,
Pei-Yin Chen, Ren-Der Chen, Yu-Pin Chang, Leang-San Shieh, Heidar A. Malki   +4 more
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Hardware Implementation and Evaluation of the HDDM

2020 International Conference on Localization and GNSS (ICL-GNSS), 2020
Interferences can significantly degrade the performance of global navigation satellite system (GNSS) receivers. Therefore, mitigation methods are required to ensure reliable operations. However, as there are different types of interferences, robust, multi-purpose mitigation algorithms are needed.
Fabio Garzia, Johannes Rossouw van der Merwe, Alexander Rügamer, Wolfgang Felber   +3 more
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A HARDWARE IMPLEMENTATION OF THE APE100 ARCHITECTURE

International Journal of Modern Physics C, 1993
APE100 processors are based on a simple Single Instruction Multiple Data architecture optimized for the simulation of Lattice Field Theories or other complex physical systems. This paper describes the hardware implementation of the first APE100 machine.
BARTOLONI A, BASTIANELLO G, BATTISTA C, CABASINO S, MARZANO F, PAOLUCCI PS, PECH J, RAPUANO F, PANIZZI E, SARNO R, TODESCO GM, TORELLI M, TROSS W, VICINI P, CABIBBO N, FUCCI A, TRIPICCIONE, Raffaele   +16 more
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Hardware implementation of a nonlinear processor

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349), 2003
Several advanced DSP algorithms, arising in applications such as wireless communications, computer graphics, computerized tomography, and speech compression, require extensive use of nonlinear functions. We discuss a new hardware approach to high-speed computation of nonlinear functions. With this approach all of the functions needed can be regularized
Vijay K. Jain, S. Shrivastava, A. D. Snider, D. Damerow, D. Chester   +4 more
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Hardware implementation of a memory allocator

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools, 2003
It is generally felt that the complexity of system-on-chip (SOC) can only be addressed by intellectual-property (IP) based design. While IPs such as processor cores, memories, and bus controllers are being offered by many vendors, IP cores for dynamic memory management, an important task for any complex application, have been close to non-existent ...
Khushwinder Jasrotia, Jianwen Zhu
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AES Embedded Hardware Implementation

Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007
The paper presents a parallel reconfigurable hardware implementation of the AES cryptographic algorithm developed for an embedded application. This new methodology directly maps a design described in a high level language, Handel-C, to FPGA platforms. The Handel-C approach narrows the gap between performance and flexibility, and thus, reduce the risk ...
Ould-cheikh Mourad, Si-Mohamed Lotfy, Noureddine Mehallegue, Ahmed Bouridane, Camel Tanougast   +4 more
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Hardware implementations of denormalized numbers

16th IEEE Symposium on Computer Arithmetic, 2003. Proceedings., 2004
Denormalized numbers are the most difficult type of numbers to implement in floating-point units. They are so complex that some designs have elected to handle them in software rather than hardware. This has resulted in execution times in the tens of thousands of cycles, which has made denormalized numbers useless to programmers.
Eric M. Schwarz, Martin S. Schmookler, Son Dao Trong   +2 more
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