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ElasticPay: Instant Peer-to-Peer Offline Extended Digital Payment System. [PDF]

Sensors (Basel)
Reddy AVSK, Banda G.
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A secure and scalable blockchain-assisted authentication framework for decentralized IoT data management. [PDF]

Sci Rep
Iswarya G, Vennila C.
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Hardware Transactional Memory meets memory persistency

Journal of Parallel and Distributed Computing, 2018
Persistent Memory (PM) and Hardware Transactional Memory (HTM) are two recent architectural developments whose joint usage promises to drastically accelerate the performance of concurrent, data-intensive applications. Unfortunately, combining these two mechanisms using existing architectural supports is far from being trivial.
Daniel Castro 0004, Paolo Romano 0002, João Pedro Barreto 0002   +2 more
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Analysis on semantic transactional memory footprint for hardware transactional memory

IEEE International Symposium on Workload Characterization (IISWC'10), 2010
We analyze various characteristics of semantic transactional memory footprint (STMF) that consists of only the memory accesses the underlying hardware transactional memory (HTM) system has to manage for the correct execution of transactional programs.
JaeWoong Chung, Dhruva R. Chakrabarti, Chi Cao Minh   +2 more
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Lightweight hardware transactional memory profiling

Proceedings of the 24th Symposium on Principles and Practice of Parallel Programming, 2019
Programs that use hardware transactional memory (HTM) demand sophisticated performance analysis tools when they suffer from performance losses. We have developed TxSampler---a lightweight profiler for programs that use HTM. TxSampler measures performance via sampling and provides a structured performance analysis to guide intuitive optimization with a ...
Qingsen Wang, Pengfei Su 0001, Milind Chabbi, Xu Liu 0001   +3 more
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Transactional Memory: The Hardware-Software Interface

IEEE Micro, 2007
As multicore chips become ubiquitous, the need to provide architectural support for practical parallel programming is reaching critical. Conventional lock-based concurrency control techniques are difficult to use, requiring the programmer to navigate through the minefield of coarse-versus fine-grained locks, deadlock, livelock, lock convoying, and ...
Austen McDonald, Brian D. Carlstrom, JaeWoong Chung, Chi Cao Minh, Hassan Chafi, Christos Kozyrakis, Kunle Olukotun   +6 more
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Hardware Transactional Memories

2016
The initiation to have a concept of shared memory in processors has built an opportunity for thread level parallelism. In various applications, synchronization or ordering tools are utilized to have an access to shared data. Traditionally, multithreaded programming models usually suggest a set of low-level primitives, such as locks, to guarantee mutual
Arsalan Shahid, Maryam Murad, Muhammad Yasir Qadri, Nadia N. Qadri, Jameel Ahmed   +4 more
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Hardware Transactional Memory with Delayed-Committing

2015 3rd International Conference on Applied Computing and Information Technology/2nd International Conference on Computational Science and Intelligence, 2015
Transactional Memory (TM) is promising to make parallel programming easier. There have been many hardware implementations of transactional memory (HTM) proposed to improve the performance, but they still suffer from some overheads when a transaction commits or aborts.
Sekai Ichii, Saki Tashiro, Atsushi Nunome, Hiroaki Hirata, Kiyoshi Shibayama   +4 more
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Fun with hardware transactional memory

Proceedings of the 2014 ACM SIGMOD International Conference on Management of Data, 2014
Leading hardware vendors such as Intel and IBM are releasing a new generation of processor architectures that provide hardware transactional memory (HTM), a synchronization mechanisms for fast in-memory transactions. This talk will argue that HTM is not just a faster way of doing the same old latches and monitors.
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Adaptive Hybrid Transaction Processing with Hardware Transaction Memory

2019 IEEE 21st International Conference on High Performance Computing and Communications; IEEE 17th International Conference on Smart City; IEEE 5th International Conference on Data Science and Systems (HPCC/SmartCity/DSS), 2019
Many performance-sensitive software systems gain benefit from the availability of advanced hardware features, and many research works have been transited to engineering reality. For instance, restricted hardware transaction memory (HTM), a hardware feature providing hardware atomicity and isolation guarantees for transactional execution, has gained ...
Tao He, Jianxin Li 0002
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