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Improving Speculative taskloop in Hardware Transactional Memory
2021Previous work proposed and evaluated Speculative taskloop (STL) on Intel Core implementing new clauses and constructs in OpenMP. The results indicated that, despite achieving some speed-ups, there was a phenomenon called the Lost-Thread Effect that caused the performance degradation of STL parallelization.
Juan Salamanca 0001, Alexandro Baldassin
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Removal of Conflicts in Hardware Transactional Memory Systems
International Journal of Parallel Programming, 2012This paper analyzes the sources of performance losses in hardware transactional memory and investigates techniques to reduce the losses. It dissects the root causes of data conflicts in hardware transactional memory systems (HTM) into four classes of conflicts: true sharing, false sharing, silent store, and write-write conflicts.
M. M. Waliullah, Per Stenström
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TMPL: A hardware transactional memory product line
2011 International Conference on High Performance Computing & Simulation, 2011Transactional memory is regarded as a very promising technology to deal with concurrency control in future multicore and manycore systems. While a lot of software, hardware, and hybrid transactional memory implementations have been proposed and analyzed, the silver bullet still hasn't been found. The main reason is that the performance of transactional
Matthias Meier +3 more
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Version management alternatives for hardware transactional memory
Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture, 2008Transactional Memory is a promising parallel programming model that addresses the programmability issues of lock-based applications using mechanisms that are transparent to developers. Hardware Transactional Memory (HTM) implements these mechanisms in silicon to obtain better results than fine-grain locking solutions.
Marc Lupon +2 more
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Efficient execution of speculative threads and transactions with hardware transactional memory
Future Generation Computer Systems, 2014Thread-level speculation (TLS) was researched to automatically parallelize portions of serial programs for execution, and transactional memory (TM) was studied as a promising alternative of lock for parallel programming due to its simplicity. Both TLS and TM require similar underlying support.
Gongming Li +4 more
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Hardware acceleration of transactional memory on commodity systems
ACM SIGPLAN Notices, 2011Jared Casper +2 more
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Early experience with a commercial hardware transactional memory implementation
ACM SIGPLAN Notices, 2009Dave Dice, Mark Moir, Levyossi
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Hardware transactional memory: A high performance parallel programming model
Journal of Systems Architecture, 2010Dongxin Wen, Xiaozong Yang
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