Results 111 to 120 of about 449 (143)

Efficient Transaction Nesting in Hardware Transactional Memory

2010
Efficient transaction nesting is one of the ongoing challenges for hardware transactional memory. To increase efficiency of closed nesting, this paper proposes a conditional partial rollback (CPR) scheme which supports conditional partial rollback without increasing hardware complexities significantly.
Yi Liu 0013, Yangming Su, Cui Zhang, Mingyu Wu 0004, Xin Zhang, He Li, Depei Qian   +6 more
openaire   +1 more source

Hardware/hybrid transactional memory

2010 International Conference on Computer, Mechatronics, Control and Electronic Engineering, 2010
Transactional memory(TM) systems become considerable popular due to it simplifying the development of highly scalable parallel programs. The implementations of TM systems are classified into three types: hardware transactional memory (HTM), software transactional memory (STM) and hybrid transactional memory (HyTM).
null Xiang Li, null Jing Zhang, null Jun-huai Li   +2 more
openaire   +1 more source

On the power of hardware transactional memory to simplify memory management

Proceedings of the 30th annual ACM SIGACT-SIGOPS symposium on Principles of distributed computing, 2011
Dynamic memory management is a significant source of complexity in the design and implementation of practical concurrent data structures. We study how hardware transactional memory (HTM) can be used to simplify and streamline memory reclamation for such data structures.
Aleksandar Dragojevic, Maurice Herlihy, Yossi Lev, Mark Moir   +3 more
openaire   +1 more source

Lightweight Hardware Transactional Memory for GPU Scratchpad Memory

IEEE Transactions on Computers, 2018
Graphics Processing Units (GPUs) have become the accelerator of choice for data-parallel applications, enabling the execution of thousands of threads in a Single Instruction - Multiple Thread (SIMT) fashion. Using OpenCL terminology, GPUs offer a global memory space shared by all the threads in the GPU, as well as a local memory space shared by only a ...
Alejandro Villegas, Rafael Asenjo, Angeles G. Navarro, Oscar G. Plata, David R. Kaeli   +4 more
openaire   +1 more source

Split hardware transactions

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming, 2008
Transactional Memory (TM) is on its way to becoming the programming API of choice for writing correct, concurrent, and scalable programs. Hardware TM (HTM) implementations are expected to be significantly faster than pure software TM (STM); however, full hardware support for true closed and open nested transactions is unlikely to be practical.This ...
Yossi Lev, Jan-Willem Maessen
openaire   +1 more source

Improving Utilization of Hardware Signatures in Transactional Memory

IEEE Transactions on Parallel and Distributed Systems, 2013
The transactional memory (TM) paradigm promises to increase programmer productivity by making it easier to write correct parallel programs. In fulfilling this goal, a TM system should maximize its performance with limited hardware resources. Conflict detection is an essential element for maintaining correctness among concurrent transactions in a TM ...
Woojin Choi, Jeffrey T. Draper
openaire   +1 more source

Analyzing Conflicts in Hardware-Supported Memory Transactions

International Journal of Parallel Programming, 2010
In order to exploit parallel resources, most transactional memory (TM) systems execute atomic blocks concurrently and must thus be prepared for data conflicts. In the event of a conflict, a TM system must choose a policy to decide when and how to manage the resulting contention.
Arrvindh Shriraman, Sandhya Dwarkadas
openaire   +1 more source

Eliminating Cascading Stall on Hardware Transactional Memory

2015 Third International Symposium on Computing and Networking (CANDAR), 2015
Multi-core processors are equipped in almost every computer systems from smartphones to high-end server machines, and shared memory programming becomes increasingly important for programmers to utilize the multi-core systems. Lock-based thread synchronization techniques have been commonly used in parallel programming on multi-core processors.
Sho Miyake, Keisuke Mashita, Ryohei Yamada, Tomoaki Tsumura   +3 more
openaire   +1 more source

An Object-Aware Hardware Transactional Memory System

2008 10th IEEE International Conference on High Performance Computing and Communications, 2008
Transactional memory (TM) is receiving attention as a way of expressing parallelism for programming multi-core systems. As a parallel programming model it is able to avoid the complexity of conventional locking. TM can enable multi-core hardware that dispenses with conventional bus-based cache coherence, resulting in simpler and more extensible systems.
Behram Khan, Matthew Horsnell, Ian Rogers, Mikel Luján, Andrew Dinn, Ian Watson   +5 more
openaire   +1 more source

Consolidated conflict detection for hardware transactional memory

Proceedings of the 23rd international conference on Parallel architectures and compilation, 2014
Hardware Transactional Memory (HTM) promises to ease multithreaded parallel programming with uncompromised performance. Microprocessors supporting HTM implement a conflict detection mechanism to detect data access conflicts between transactions. Understanding the on-chip network bandwidth utilization of such mechanisms is important as the energy and ...
Lihang Zhao, Jeffrey T. Draper
openaire   +1 more source