Protocol for whole-cell patch-clamp recording and post hoc identification of hippocampal CA2 pyramidal neurons in adult mouse brain slices. [PDF]
STAR ProtocEngel D, Nguyen L.
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Experimental Platform for Screening and Validation of BacNa<sub>v</sub> Gene Therapy Candidates. [PDF]
Circ Arrhythm ElectrophysiolWu T, Nguyen HX, Siu YY, Li Y, Bursac N.
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Process parameters optimization of sweet orange juice ohmic heat-assisted vacuum evaporation and assessment of concentrate quality. [PDF]
BMC BiotechnolVangapandu VR, Bitra VSP.
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Digital OTAs: Conventional Designs Versus Emerging Concept
Akbari M, Covi E, Gibertini P.
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Tunable Holding-Voltage High Voltage ESD Devices
2019 IEEE International Reliability Physics Symposium (IRPS), 2019Physical understanding of the interaction of junction depth and the location of different Drain-side N-type implants on the holding-voltage of LDNMOS is presented. Using N-type well implants to modulate the junction depth, width and doping concentration results in change of the holding-voltage of LDMOS since the drain potential is a function of ...
Jian-Hsing Lee, Natarajan Mahadeva Iyer
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Precision analog integrator with voltage hold
Review of Scientific Instruments, 2007In some applications, like a magnetization and demagnetization of ordinary and superconducting magnets driven by the voltage controlled current sources, it is desirable to change the voltage smoothly and linearly toward an adjusted value and then hold this value in time. A circuit is presented that allows: (i) the slow, smooth, and linear change of the
Holt, Stephen, Skyba, Peter
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A Switched-Voltage High-Accuracy Sample/Hold Circuit
APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 2004In this paper, three switched-voltage (SV) sample/hold (S/H) circuits are presented to compensate for clock-feed-through (CFT) and channel-length modulation effect. They consist of a CMOS SV-delay cell. Thus, the configuration is very simple. The proposed circuits can be operated using simple nonoverlapping two phase clocks. The performance is verified
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Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration
APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, 2008In high voltage (HV) ICs, the latch-up immunity of HV devices is often referred to the TLP-measured holding voltage because the huge power generated from DC curve tracer can easily damage HV device during measurement. An n-channel lateral DMOS (LDMOS) was fabricated in a 0.25-mum 18-V bipolar CMOS DMOS (BCD) process to investigate the validity of TLP ...
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Voltage Holding Prediction in Multi Electrode-multi Voltage Systems Insulated in Vacuum
IEEE Transactions on Dielectrics and Electrical Insulation, 2010-
Pilan N, Veltri P, De Lorenzi A
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