Results 251 to 260 of about 72,792 (298)
Some of the next articles are maybe not open access.
A CMOS Structure with high latchup holding voltage
IEEE Electron Device Letters, 1984Latchup free operation is demonstrated in CMOS by attaining holding voltages in excess of V dd (5V). A thin epitaxial layer over a heavily doped substrate together with butted background contact at transistor sources is shown to be an effective structure to control the parasitic bipolar latchup.
G.J. Hu, R.H. Bruce
openaire +1 more source
2019 International Conference on Electronics, Information, and Communication (ICEIC), 2019
In this paper, 2-stage Electrostatic Discharge (ESD) protection circuit with high holding voltage and low trigger voltage for high voltage applications is proposed. As semiconductor densities have increased, ESD has become a serious problem in semiconductor processes.
Byung-Seok Lee +4 more
openaire +1 more source
In this paper, 2-stage Electrostatic Discharge (ESD) protection circuit with high holding voltage and low trigger voltage for high voltage applications is proposed. As semiconductor densities have increased, ESD has become a serious problem in semiconductor processes.
Byung-Seok Lee +4 more
openaire +1 more source
Microelectronics Reliability, 2015
Abstract An LDNMOS-based and an LDPMOS-based dual direction silicon controlled rectifier (DDSCR) devices have been designed and fabricated in a 0.5-μm 5 V/18 V high voltage (HV) CDMOS process. These devices can be used to protect pins with a voltage range that goes above and below the ground by discharging electrostatic current in both positive and ...
Yang Wang 0105 +4 more
openaire +1 more source
Abstract An LDNMOS-based and an LDPMOS-based dual direction silicon controlled rectifier (DDSCR) devices have been designed and fabricated in a 0.5-μm 5 V/18 V high voltage (HV) CDMOS process. These devices can be used to protect pins with a voltage range that goes above and below the ground by discharging electrostatic current in both positive and ...
Yang Wang 0105 +4 more
openaire +1 more source
Dielectric characterization and voltage holding ratio of blue-phase cells
Displays, 2016Abstract The phase behaviors of a blue-phase (BP) liquid crystal in a planar-aligned cell were investigated by means of temperature-dependent dielectric spectroscopy. With auxiliary observations of optical transmission spectra and birefringent textures, we found that the transition temperatures of two adjacent mesophases, including the cholesteric-to-
Po-Chang Wu +3 more
openaire +1 more source
High voltage holding in the negative ion sources with cesium deposition
Review of Scientific Instruments, 2015High voltage holding of the large surface-plasma negative ion source with cesium deposition was studied. It was found that heating of ion-optical system electrodes to temperature >100 °C facilitates the source conditioning by high voltage pulses in vacuum and by beam shots.
Yu, Belchenko +4 more
openaire +2 more sources
A CMOS low-voltage fully differential sample-and-hold circuit
APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, 2008A new technique for realizing a CMOS low-voltage fully differential sample-and-hold circuit is presented. A low-voltage technique is proposed for CMOS sample-and-hold circuit that avoids the use of low-threshold voltage process, on-chip clock voltage doubler, bootstrapped switch, or switched-opamp technique.
Chi-Chang Lu +2 more
openaire +1 more source
A Modified LDMOS-SCR with High Holding Voltage for high voltage ESD Protection
2019 8th International Symposium on Next Generation Electronics (ISNE), 2019A modified lateral DMOS-SCR with high holding voltage for electrostatic discharge (ESD) protection applications has been proposed in this paper. The proposed MLDMOS-SCR possesses a lower trigger voltage as well as a higher holding voltage, which is very suitable for 18V/20V ESD applications.
Wenqiang Song, Zhiwei Liu, Juin J. Liou
openaire +1 more source
2012 25th International Symposium on Discharges and Electrical Insulation in Vacuum (ISDEIV), 2012
In the framework of the program for the construction in Padova - Italy of the first prototype of the ITER 1 MeV-16 MW Negative Neutral Beam Injector a R&D program on voltage holding in vacuum has been initiated since 2009, aimed at supporting the design, construction and development of the NNBI accelerator.
A De Lorenzi, N Pilan, A Pesce, E Spada
openaire +2 more sources
In the framework of the program for the construction in Padova - Italy of the first prototype of the ITER 1 MeV-16 MW Negative Neutral Beam Injector a R&D program on voltage holding in vacuum has been initiated since 2009, aimed at supporting the design, construction and development of the NNBI accelerator.
A De Lorenzi, N Pilan, A Pesce, E Spada
openaire +2 more sources
Characterization of X-ray Events for a Vacuum High Voltage Holding Experiment
2020 29th International Symposium on Discharges and Electrical Insulation in Vacuum (ISDEIV), 2021The High Voltage Padova Test Facility (HVPTF) is an experimental device for investigating HV insulation in vacuum, in support of the realization of MITICA, the prototype of a neutral beam injector for ITER. The facility investigates the physical phenomena underlying voltage holding in vacuum, such as the mechanisms causing breakdowns and the electrode ...
S. Spagnolo +18 more
openaire +5 more sources
Holding voltage adjustable silicon controlled rectifier
2008 31st International Spring Seminar on Electronics Technology, 2008Holding voltage adjustable Silicon Controlled Rectifier (HVASCR) is a SCR with possibility to tune the holding voltage. The HVASCR structure forms good ESD (electrostatic discharge) protection. Such structures act as a protection of integrated circuits against parasitic electrostatic discharge. The use of such structures provides ICs robustness against
openaire +1 more source