Results 271 to 280 of about 72,792 (298)

A physical model for the correlation between holding voltage and holding current in epitaxial CMOS latch-up

IEEE Electron Device Letters, 1998
A new physical model concerning the holding points for latch-up in epitaxial CMOS structures is established by combining the lateral p-i-n high level injection and the vertical BJT base push-out formula. The model matches adequately the correlation between holding voltage and holding current extensively measured from different combinations of ...
null Ming-Jer Chen, null Hun-Shung Lee, null Jyh-Huei Chen, null Chin-Shan Hou, null Chaun-Sheng Lin, null Yeh-Ning Jou   +5 more
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3D Approaches to Engineer Holding Voltage of SCR

2023 IEEE International Reliability Physics Symposium (IRPS), 2023
Satendra Kumar Gautam, Harsha B. Variar, Juan Luo, Ning Shi, David Marreiro, Shekar Mallikarjunaswamy, Mayank Shrivastava   +6 more
openaire   +1 more source

The novel SCR-based ESD protection device with high holding voltage

2009 IEEE International Symposium on Circuits and Systems, 2009
This paper introduces a novel silicon controlled rectifier (SCR)-based device for ESD power clamp and I/O clamp. The device obtained the high holding voltage and low triggering voltage by adding a p-drift junction and n-well in the cathode region. These characteristics enable latch-up immune normal operation as well as superior full chip ESD protection.
Jong-Il Won, Samuell Shin, Ka-San Ha, Jong-Ki Kwon, Yong-Seo Koo   +4 more
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Magnetic insulation to improve voltage holding in electrostatic accelerators

Physics of Plasmas, 2009
Voltage holding in high voltage electrostatic accelerators is a longstanding problem which limits the practically obtainable performance of most systems. This paper proposes an idea for improving the voltage holding in electrostatic accelerators by suppressing breakdowns between successive stages of an accelerator. The idea consists of flowing electric
openaire   +1 more source

A fully balanced programmable sample-hold amplifier for low-voltage applications

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), 2002
In this paper, we propose a CMOS fully balanced sample-hold amplifier. The proposed circuit is based on the technique described by Goncalves et al. (1996), which is appropriate for low voltage operation. The programmability of the sample-hold circuit is achieved via the MOSFET Only Current Divider (MOCD).
Fathi A. Farag, Márcio C. Schneider, Carlos Galup-Montoro   +2 more
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A precise sample-and-hold circuit topology in CMOS for low voltage applications with offset voltage self correction

9th International Conference on Electronics, Circuits and Systems, 2003
This work describes a new topology for CMOS sample-and-hold circuits in low voltage with self-correction of the offset voltage caused by mismatches in the differential input pair of the operational amplifier. The charge injection of the NMOS switches, although not properly modeled by the simulators, is an important factor and it is minimized in this ...
Luis Henrique de Carvalho Ferreira, Robson L. Moreno, Tales C. Pimenta, Carlos A. R. Filho   +3 more
openaire   +1 more source

A class-AB very low voltage amplifier and sample & hold circuit

2011 20th European Conference on Circuit Theory and Design (ECCTD), 2011
In this paper we present a low-power low-voltage class-AB amplifier with rail-to-rail output swing capable of operating from 0.5V to 1.0V of supply voltage, and two Sample & Hold (SHA) circuits based on this amplifier. The bias current and the bandwidth of the amplifier depend on the voltage supply, so that for low-power operation a low supply voltage ...
CENTURELLI, Francesco, MONSURRO', PIETRO, TRIFILETTI, Alessandro   +2 more
openaire   +1 more source

Vacuum High Voltage Holding: DC Experiments and modelling [PDF]

, 2019
This report describes the activities carried out within the subtask T5.7 of the Work Programme WP2019 at the High Voltage Padova Test Facility HVPTF and on the new High Voltage Short Gap Test Facility HVSGTF. The activities mainly consisted in: 1) Test of two electrodes with double-polarity configurations (Common Mode Voltage tests).
Pilan N., Barbato P., Baseggio L., Battistella M., Bernardi M., Carraro M., Cavazzana R., Cervaro V., Cinetto P., De Lorenzi A., Fincato M., Fontana C., Friso D., Gobbo G., Grosso B., Laterza L., Lotto L., Manduchi G., Maniero M., Muraro A., Martines E., Mc Cormack O., Migliorato L., Moretti M., Nobili P., Patton T., Pesavento G., Pino F., Polato S., Rigoni A., Rigamonti D., Rizzieri R., Romanato L., Rossetto F., Spada E., Spagnolo S., Taliercio C., Tiso A., vignando M., Zuin M.   +39 more
openaire  

Vacuum High Voltage Holding: DC Experiments and modelling

2018
This report describes the main activities carried out at the High Voltage Padova Test Facility HVPTF in 2018 and the ones related to the installation of a new high voltage test stand at the Consorzio RFX . The activities of the subtask 5.7 have been carried out according with the Work Programme (WP) 2018 between F4E and the Consorzio RFX, agreement on ...
Pilan n., Lotto L., De Lorenzi A., Spagnolo S., Fincato M., Cervaro V., Franchin L., Maniero M., Romanato L., Battistella M., Spada E., Rossetto F., Pesavento G., Gobbo R., Taliercio C., Martines E., Zuin M., Fontana C., Plinio F., Barbato P., Nobili P., Migliorato L., Carraro M., Patton T., Polato S., Moretti M., Friso D., Bernardi M., Tiso A., Laterza B.   +29 more
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Voltage holding and self-discharge phenomenon in ZnO-Co3O4 core-shell heterostructure for binder-free symmetric supercapacitors

Chemical Engineering Journal, 2022
Rajneesh Kumar Mishra, Gyu Jin Choi, Jay Singh   +2 more
exaly