Results 241 to 250 of about 434,022 (280)

Error Control Scheme of Hybrid ARQ Based on Majority Voting Bit by Bit

2009
A hybrid ARQ scheme based on the conception of majority voting for binary linear block codes over AWGN channel is presented. At each transmission, the received word is kept in memory buffers. After a number of receptions, the decoding process first determines each bit as 1 or 0 based on the majority of the corresponding bits in the received words.
Hsin-Kun Lai, Chia-Chin Ma, Erl-Huei Lu
openaire   +1 more source

Design and implementation of hybrid 4-bit flash ADC

2016 International Conference on Advances in Computing, Communications and Informatics (ICACCI), 2016
This research presents low power Hybrid 4bit flash ADC. This 4bit Hybrid Flash ADC is Designed by series of resistance, 2(n−1) comparator and MUX based encoder. The hybrid 4 bit Flash ADC was designed and simulated in 90nm technology using a Cdesigner tool with 1.2 V supply and 1GHz frequency.
Kriti Thakur, Sandeep Kaur Kingra
openaire   +1 more source

Bit-by-Bit Pipelined and Hybrid-Grained 2D Architecture for Motion Estimation of H.264/AVC

Journal of Signal Processing Systems, 2011
In H.264/AVC, the motion estimation (ME) routine supports variable block size and involves highly parallel sum of absolute difference (SAD) computations. In this study, we introduce a bit serial hybrid-grained processing element (PE) based 2D architecture that has both early termination and intensive data reuse capabilities.
Yang Song 0007, Ali Akoglu
openaire   +1 more source

Hybrid Method as Pseudo-Random Bits Generator

2019 First International Conference of Computer and Applied Sciences (CAS), 2019
This paper aims to combine among Exponential chaotic map, Linear Congruential Generators (LCG), Multiplicative Congruential Generators (MCG) and RIPEMD-160 to create new pseudo arbitrary number generator. The guideline of the proposed technique involves generating key sequences by Exponential chaotic map to be utilised as coefficients in Linear ...
Mohammed M. Al-Mhadawi, Akhlas A. Albahrani   +1 more
openaire   +1 more source

An Analysis of the Performance of PDC Hybrid Drill Bits

SPE/IADC Drilling Conference, 1987
ABSTRACT This paper details the results of a project to extend the range of PDC bit applications to harder non-uniform formations. These formations had previously proved difficult to drill with PDC. The resulting design concept is outlined and the targeted formations, field operating parameters and performances are ...
J.L. Williams, A.I. Thompson
openaire   +1 more source

A low bit rate hybrid wavelet-DCT video codec

IEEE Transactions on Circuits and Systems for Video Technology, 2005
A hybrid video codec, where the intraframe pictures are wavelet-based coded and the interframe pictures are coded with a standard H.263 codec is proposed. We show that intraframe-wavelet coded pictures not only improve the quality of I-pictures but also result in lower distorted prediction pictures that outperforms a pure H.263 video codec.
Reza Dianat, M. Ghanbari 0001, Farrokh Marvasti   +2 more
openaire   +1 more source

A Hybrid Model for Optimal Pseudorandom Bit Sequence Generation

2019
Chaotic map gained its importance in the field of cryptography, due to its properties like, randomness, unpredictability, sensitivity on initial condition, aperiodicity, which is used to generate pseudorandom bit streams. In this paper the optimal values of chaos parameters are generated through Real Coded Genetic Algorithm (RCGA), which is optimal ...
Ramen Pal, Somnath Mukhopadhyay
openaire   +1 more source

Design of Low Power 5-Bit Hybrid Flash ADC

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016
In this paper, a low power 5-bit hybrid flasharchitecture is proposed. The proposed analog-to-digital con-verter (ADC) uses appropriate combination of both conventionaldouble-tail comparators and standard cell comparators. Stan-dard cell comparators are used to reduce power consumption.
S. M. Mayur, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha   +3 more
openaire   +1 more source

A hybrid codec for very low bit rate video coding

Proceedings of 3rd IEEE International Conference on Image Processing, 2002
In segmentation based video compression algorithms, the quality of the segmentation and the efficiency of the boundary coding have strong influence on the coding efficiency and image quality. We propose a hybrid codec using motion segmentation and employing a variable size block structure.
Kui Zhang, Miroslaw Bober, Josef Kittler
openaire   +1 more source

Bit Error Rate Analysis of Analog and Hybrid Beamforming Techniques

2019 IEEE 17th International Symposium on Intelligent Systems and Informatics (SISY), 2019
The objective of this paper is to compare the two beamforming techniques that will come into use for the deployment of 5th generation communication networks. This is a side by side comparison of analog and hybrid beamforming which is said to be the main techniques that have been suggested by industry specialists over the past couple of years. Bit Error
Srikanth Kamath, Shawn Ivan D'souza
openaire   +1 more source