Results 251 to 260 of about 434,022 (280)

Exploring Tag-Bit Memory Operations in Hybrid Memory Cubes

Proceedings of the Second International Symposium on Memory Systems, 2016
The recent advances in multi-dimensional or stacked memory devices have led to a significant resurgence in research and effort associated with exploring more expressive memory operations in order to improve application throughput. The goal of these efforts is to provide memory operations in the logic layer of a stacked device that provide pseudo ...
John D. Leidel, Yong Chen 0001
openaire   +1 more source

Fast Low-Power 64-Bit Modular Hybrid Adder

2005
This paper presents the design of a new dynamic addition circuit based on a hybrid ripple-carry/carry-look-ahead/carry-bypass approach. In order to reduce power, the usage of duplicated carry-select stages is avoided. High computational speed is reached thanks to the implemented two-phase running. The latter makes the proposed adder able to exploit the
PERRI, Stefania, CORSONELLO, Pasquale, COCORULLO, Giuseppe   +2 more
openaire   +2 more sources

4800 and 7200 bit/sec hybrid codebook multipulse coding

International Conference on Acoustics, Speech, and Signal Processing, 2003
The authors describe a low-complexity coding technique that combines multipulse and stochastic excitation. The system, known as hybrid multipulse coding (HMC), provides good quality at 4.8 and 7.2 kb/s. HMC uses efficient pulse excitation for voiced speech and stochastic excitation for unvoiced speech.
Richard L. Zinser, Steven R. Koch
openaire   +1 more source

A hybrid scheme for low bit-rate coding of stereo images

IEEE Transactions on Image Processing, 2002
In this paper, we propose a hybrid scheme to implement an object driven, block based algorithm to achieve low bit-rate compression of stereo image pairs. The algorithm effectively combines the simplicity and adaptability of the existing block based stereo image compression techniques with an edge/contour based object extraction technique to determine ...
Jianmin Jiang, Eran A. Edirisinghe
openaire   +2 more sources

Review and Implementation of 1-Bit Adder in CMOS and Hybrid Structures

2020
Different adder structures have been reviewed with CMOS logic and hybrid logic styles in this paper. XOR/XNOR cell, which is the key element in full adder design was also reviewed. Hybrid adders have advantage of low delay and low area occupancy due to less transistor count used. Lower value of PDP also can be achieved with hybrid structures.
Bhaskara Rao Doddi, V. Leela Rani
openaire   +1 more source

The Algorithm and Circuit Design of a 400MHz 16-Bit Hybrid Multiplier

2006
In this paper we present the algorithm of a 16-bit hybrid multiplier, which can work in two modes. In normal mode, it performs a 16-bit multi-plication. In SIMD mode, it performs two parallel 8-bit multiplications. The proposed algorithm is based on the raix-4 modified Booth's algorithm.
Zhentao Li, Shuming Chen, Zhao-Liang Li, Conghua Lei   +3 more
openaire   +1 more source

A 13-bit Hybrid Interpolated SAR ADC

2021 6th International Conference on Integrated Circuits and Microsystems (ICICM), 2021
Yiqun Wang, Peng Miao, Fei Li, Huan Wang, Bowen Ding, Weiqi Gu   +5 more
openaire   +1 more source

Bit rate control for hybrid DPCM/DCT video codec

IEEE Transactions on Circuits and Systems for Video Technology, 1994
This paper presents a simple approach to regulating the bit stream generated by the hybrid DPCM/DCT video codec so that the compressed bit stream at a variable rate can be transmitted over a fixed rate channel. Bit rate regulation is accomplished by appropriately quantizing the DCT coefficients where the quantization stepsize is obtained by multiplying
openaire   +1 more source

Failure resistance research of the dual-stage hybrid bit

Engineering Failure Analysis, 2023
Deng Zhang
exaly  

Torsion and vibration reduction mechanism of roller PDC hybrid bit

Journal of Petroleum Science and Engineering, 2022
Kuilin Huang, Yuntian Wang, Shiwei Niu   +2 more
exaly