Software/Hardware Co-Verification for Custom Instruction Set Processors
IEEE Access, 2021 Verification of software and processor hardware usually proceeds separately, software analysis relying on the correctness of processors executing machine instructions.
Marie-Christine Jakobs +4 more
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An Instruction Set Extension to Support Software-Based Masking
Transactions on Cryptographic Hardware and Embedded Systems, 2021 In both hardware and software, masking can represent an effective means of hardening an implementation against side-channel attack vectors such as Differential Power Analysis (DPA).
Si Gao +5 more
doaj +1 more source
Design of Ultra-Low-Power RISC-V Dedicated Processor for IToF Sensor [PDF]
Jisuanji gongcheng, 2022 Indirect Time of Flight(IToF) depth detection technology is one of the current mainstream solutions to realize 3D perception.The core component of this technology is the IToF sensor chip.With the acceleration of digitization and intellectualization, the ...
HUANG Zhengwei, LIU Hongwei, XU Yuan
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RISC-V Instruction Set Extensions for Lightweight Symmetric Cryptography
Transactions on Cryptographic Hardware and Embedded Systems, 2022 The NIST LightWeight Cryptography (LWC) selection process aims to standardise cryptographic functionality which is suitable for resource-constrained devices.
Hao Cheng +4 more
doaj +1 more source
Design and implementation of hardware-based dynamic instruction set randomization framework
网络与信息安全学报, 2017 All the existing ISR methods have some defects including stripping data from code segment is hard to accomplish,static ISR has fixed key and pseudo-random key is not secure.To introduce ISR technology into the se-curity protection of kernel layer and ...
San DU,Hui SHU,Fei KANG
doaj +3 more sources
QFEC ASIP: A Flexible Quad-Mode FEC ASIP for Polar, LDPC, Turbo, and Convolutional Code Decoding
IEEE Access, 2018 In this paper, we extend polar decoding function to our previous design, and propose a flexible quad-mode forward error correction application specific instruction-set processor (QFEC ASIP) that supports polar, low-density parity-check (LDPC), turbo, and
Wan Qiao, Dake Liu, Shaohan Liu
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Masked Accelerators and Instruction Set Extensions for Post-Quantum Cryptography
Transactions on Cryptographic Hardware and Embedded Systems, 2021 Side-channel attacks can break mathematically secure cryptographic systems leading to a major concern in applied cryptography. While the cryptanalysis and security evaluation of Post-Quantum Cryptography (PQC) have already received an increasing research
Tim Fritzmann +6 more
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Special Instruction Set Processor for Convolutional Neural Network Based on RISC-V [PDF]
Jisuanji gongcheng, 2021 The x86-based and ARM-based CPU are limited by the patent authorization,which increases their customization cost and reduces the flexibility.To address the problem,this paper chooses the open-source instruction set architecture,RISC-V,to build an special
LIAO Hansong, WU Zhaohui, LI Bin
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An NFC on Two-Coil WPT Link for Implantable Biomedical Sensors under Ultra-Weak Coupling
Sensors, 2017 The inductive link is widely used in implantable biomedical sensor systems to achieve near-field communication (NFC) and wireless power transfer (WPT). However, it is tough to achieve reliable NFC on an inductive WPT link when the coupling coefficient is
Chen Gong +4 more
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A Magnetic-Balanced Inductive Link for the Simultaneous Uplink Data and Power Telemetry
Sensors, 2017 When using the conventional two-coil inductive link for the simultaneous wireless power and data transmissions in implantable biomedical sensor devices, the strong power carrier could overwhelm the uplink data signal and even saturate the external uplink
Chen Gong +3 more
doaj +1 more source