Results 21 to 30 of about 9,050,905 (317)
An Instruction Set Extension to Support Software-Based Masking
Transactions on Cryptographic Hardware and Embedded Systems, 2021 In both hardware and software, masking can represent an effective means of hardening an implementation against side-channel attack vectors such as Differential Power Analysis (DPA).
Si Gao +5 more
doaj +1 more source
PMC-VQA: Visual Instruction Tuning for Medical Visual Question Answering [PDF]
arXiv.org, 2023 Medical Visual Question Answering (MedVQA) presents a significant opportunity to enhance diagnostic accuracy and healthcare delivery by leveraging artificial intelligence to interpret and answer questions based on medical images.
Xiaoman Zhang +6 more
semanticscholar +1 more source
Design of Ultra-Low-Power RISC-V Dedicated Processor for IToF Sensor [PDF]
Jisuanji gongcheng, 2022 Indirect Time of Flight(IToF) depth detection technology is one of the current mainstream solutions to realize 3D perception.The core component of this technology is the IToF sensor chip.With the acceleration of digitization and intellectualization, the ...
HUANG Zhengwei, LIU Hongwei, XU Yuan
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Text-to-Audio Generation using Instruction-Tuned LLM and Latent Diffusion Model [PDF]
arXiv.org, 2023 The immense scale of the recent large language models (LLM) allows many interesting properties, such as, instruction- and chain-of-thought-based fine-tuning, that has significantly improved zero- and few-shot performance in many natural language ...
Deepanway Ghosal +3 more
semanticscholar +1 more source
QFEC ASIP: A Flexible Quad-Mode FEC ASIP for Polar, LDPC, Turbo, and Convolutional Code Decoding
IEEE Access, 2018 In this paper, we extend polar decoding function to our previous design, and propose a flexible quad-mode forward error correction application specific instruction-set processor (QFEC ASIP) that supports polar, low-density parity-check (LDPC), turbo, and
Wan Qiao, Dake Liu, Shaohan Liu
doaj +1 more source
Special Instruction Set Processor for Convolutional Neural Network Based on RISC-V [PDF]
Jisuanji gongcheng, 2021 The x86-based and ARM-based CPU are limited by the patent authorization,which increases their customization cost and reduces the flexibility.To address the problem,this paper chooses the open-source instruction set architecture,RISC-V,to build an special
LIAO Hansong, WU Zhaohui, LI Bin
doaj +1 more source
IACR Cryptology ePrint Archive, 2020 In this paper, we present an instruction set coprocessor architecture for lattice-based cryptography and implement the module lattice-based post-quantum key encapsulation mechanism (KEM) Saber as a case study.
S. Roy, Andrea Basso
semanticscholar +1 more source
Design and implementation of hardware-based dynamic instruction set randomization framework
网络与信息安全学报, 2017 All the existing ISR methods have some defects including stripping data from code segment is hard to accomplish,static ISR has fixed key and pseudo-random key is not secure.To introduce ISR technology into the se-curity protection of kernel layer and ...
San DU, Hui SHU, Fei KANG
doaj +3 more sources
An NFC on Two-Coil WPT Link for Implantable Biomedical Sensors under Ultra-Weak Coupling
Sensors, 2017 The inductive link is widely used in implantable biomedical sensor systems to achieve near-field communication (NFC) and wireless power transfer (WPT). However, it is tough to achieve reliable NFC on an inductive WPT link when the coupling coefficient is
Chen Gong +4 more
doaj +1 more source
A Magnetic-Balanced Inductive Link for the Simultaneous Uplink Data and Power Telemetry
Sensors, 2017 When using the conventional two-coil inductive link for the simultaneous wireless power and data transmissions in implantable biomedical sensor devices, the strong power carrier could overwhelm the uplink data signal and even saturate the external uplink
Chen Gong +3 more
doaj +1 more source