Results 21 to 30 of about 1,515,607 (318)
For an inductive wireless power transfer (IWPT) system, maintaining a reasonable power transfer efficiency and a stable output power are two most challenging design issues, especially when coil distance varies.
Zhidong Miao, Dake Liu, Chen Gong
doaj +1 more source
A scalable ASIP for BP Polar decoding with multiple code lengths
In this paper, we propose a flexible scalable BP Polar decoding application-specific instruction set processor (PASIP) that supports multiple code lengths (64 to 4096) and any code rates.
Qiao Wan, Liu Dake
doaj +1 more source
On algorithmic equivalence of instruction sequences for computing bit string functions [PDF]
Every partial function from bit strings of a given length to bit strings of a possibly different given length can be computed by a finite instruction sequence that contains only instructions to set and get the content of Boolean registers, forward jump ...
Bergstra, J. A., Middelburg, C. A.
core +2 more sources
The design of scalar AES Instruction Set Extensions for RISC-V
Secure, efficient execution of AES is an essential requirement on most computing platforms. Dedicated Instruction Set Extensions (ISEs) are often included for this purpose. RISC-V is a (relatively) new ISA that lacks such a standardized ISE.
Ben Marshall +4 more
doaj +3 more sources
Audio Denoising Coprocessor Based on RISC-V Custom Instruction Set Extension
As a typical active noise control algorithm, Filtered-x Least Mean Square (FxLMS) is widely used in the field of audio denoising. In this study, an audio denoising coprocessor based on Retrenched Injunction System Computer-V (RISC-V), a custom ...
Jun Yuan +5 more
doaj +1 more source
Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms
The ever-increasing need for securing computing systems using cryptographic algorithms is spurring interest in the efficient implementation of common algorithms.
Görkem Nişancı +2 more
doaj +1 more source
Analysis on the Possibility of RISC-V Adoption [PDF]
As the interface between hardware and software, Instruction Set Architectures (ISAs) play a key role in the operation of computers. While both hardware and software have continued to evolve rapidly over time, ISAs have undergone minimal change. Since its
Scott, Ian
core
Virtual Machine Support for Many-Core Architectures: Decoupling Abstract from Concrete Concurrency Models [PDF]
The upcoming many-core architectures require software developers to exploit concurrency to utilize available computational power. Today's high-level language virtual machines (VMs), which are a cornerstone of software development, do not provide ...
A. Peymandoust +56 more
core +3 more sources
Function-call Instruction Characteristic Analysis Based Instruction Set Architecture Recognization Method for Firmwares [PDF]
The recognition of instruction set architecture is a crucial task for conducting security research on embedded devices,and has significant implications.However,existing studies and tools often suffer from low recognition accuracy and high false positive ...
JIA Fan, YIN Xiaokang, GAI Xianzhe, CAI Ruijie, LIU Shengli
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To examine the effects of combined positive verbal encouragement and general technical guidelines on technical and psychophysiological parameters in pupils during a small-sided handball passing game.
Feten Sahli +8 more
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