Results 21 to 30 of about 1,478,008 (318)
Sensors, 2017 For an inductive wireless power transfer (IWPT) system, maintaining a reasonable power transfer efficiency and a stable output power are two most challenging design issues, especially when coil distance varies.
Zhidong Miao, Dake Liu, Chen Gong
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A scalable ASIP for BP Polar decoding with multiple code lengths
MATEC Web of Conferences, 2018 In this paper, we propose a flexible scalable BP Polar decoding application-specific instruction set processor (PASIP) that supports multiple code lengths (64 to 4096) and any code rates.
Qiao Wan, Liu Dake
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On algorithmic equivalence of instruction sequences for computing bit string functions [PDF]
, 2014 Every partial function from bit strings of a given length to bit strings of a possibly different given length can be computed by a finite instruction sequence that contains only instructions to set and get the content of Boolean registers, forward jump ...
Bergstra, J. A., Middelburg, C. A.
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Instruction set compiled simulation [PDF]
Proceedings of the 40th annual Design Automation Conference, 2003 Instruction set simulators are critical tools for the exploration and validation of new programmable architectures. Due to increasing complexity of the architectures and time-to-market pressure, performance is the most important feature of an instruction-set simulator.
Prabhat Mishra +2 more
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The design of scalar AES Instruction Set Extensions for RISC-V
Transactions on Cryptographic Hardware and Embedded Systems, 2020 Secure, efficient execution of AES is an essential requirement on most computing platforms. Dedicated Instruction Set Extensions (ISEs) are often included for this purpose. RISC-V is a (relatively) new ISA that lacks such a standardized ISE.
Ben Marshall +4 more
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Audio Denoising Coprocessor Based on RISC-V Custom Instruction Set Extension
Acoustics, 2022 As a typical active noise control algorithm, Filtered-x Least Mean Square (FxLMS) is widely used in the field of audio denoising. In this study, an audio denoising coprocessor based on Retrenched Injunction System Computer-V (RISC-V), a custom ...
Jun Yuan +5 more
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Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms
Cryptography, 2022 The ever-increasing need for securing computing systems using cryptographic algorithms is spurring interest in the efficient implementation of common algorithms.
Görkem Nişancı +2 more
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Virtual Machine Support for Many-Core Architectures: Decoupling Abstract from Concrete Concurrency Models [PDF]
, 2010 The upcoming many-core architectures require software developers to exploit concurrency to utilize available computational power. Today's high-level language virtual machines (VMs), which are a cornerstone of software development, do not provide ...
A. Peymandoust +56 more
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Automatic Vectorization Transplant and Optimization of LLVM for Domestic Processors [PDF]
Jisuanji gongcheng, 2022 Automatic vectorization is essential in SIMD extension vectorization, and has been implemented in the LLVM compiler.However, the difference of vector length and instruction set functions can cause the domestic processors to lose the opportunity of ...
LI Jia'nan, HAN Lin, CHAI Yunda
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Analysis on the Possibility of RISC-V Adoption [PDF]
, 2020 As the interface between hardware and software, Instruction Set Architectures (ISAs) play a key role in the operation of computers. While both hardware and software have continued to evolve rapidly over time, ISAs have undergone minimal change. Since its
Scott, Ian
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