Results 41 to 50 of about 1,478,008 (318)
Instruction Set Architectures for Quantum Processing Units
Progress in quantum computing hardware raises questions about how these devices can be controlled, programmed, and integrated with existing computational workflows.
AR Calderbank +3 more
core +1 more source
Formal verification of a software countermeasure against instruction skip attacks [PDF]
Fault attacks against embedded circuits enabled to define many new attack paths against secure circuits. Every attack path relies on a specific fault model which defines the type of faults that the attacker can perform.
Encrenaz, Emmanuelle +3 more
core +6 more sources
Bear management changes management actions according to the horizontal axis of the population size and the vertical axis of the number of nuisance bears. Aiming for the target population size of Ntar, Actions I and II protect the bears, and Action IV reduces the population.
Hiroyuki Matsuda +5 more
wiley +1 more source
Optimizing the SICStus Prolog virtual machine instruction set [PDF]
The Swedish Institute of Computer Science (SICS) is the vendor of SICStus Prolog. To decrease execution time and reduce space requirements, variants of SICStus Prolog's virtual instruction set were investigated.
Nässén, Henrik
core +2 more sources
An instruction set and microarchitecture for instruction level distributed processing [PDF]
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulators at the top. The instruction stream is divided into chains of dependent instructions (strands) where intra-strand dependences are passed through the accumulator.
James E. Smith, Ho-Seop Kim
openaire +2 more sources
Population size and dynamics fundamentally shape speciation by influencing genetic drift, founder events, and adaptive potential. Small populations may speciate rapidly due to stronger drift, whereas large populations harbor more genetic diversity, which can alter divergence trajectories. We highlight theoretical models that incorporate population size
Ryo Yamaguchi +3 more
wiley +1 more source
Compiler Optimization of Wide Memory Access for Aarch64
The popularity of ARM-based processors in HPC and cloud computing is gradually increasing and the development of compilers and code optimizations is important to achieve better use of hardware resources.
Viacheslav Chernonog +2 more
doaj +1 more source
Design and Implementation of RISC-Ⅴ Extended Ⅰnstruction Set Supporting FPGA Dynamic Reconfiguration [PDF]
Currently, dynamic refactoring is implemented by configuring it through on-chip interfaces, usually using the dynamic refactoring control Intellectual Property (IP) core provided by the official Field Programmable Gate Array (FPGA), and connected to the ...
ZHOU Xuanjin, CAI Gang, HUANG Zhihong
doaj +1 more source
Instruction Set Extension of a RiscV Based SoC for Driver Drowsiness Detection
This paper describes the design and implementation of a driver drowsiness detection (DDD) system using a modified RiscV processor on a field-programmable gate array (FPGA).
Seyed Kian Mousavikia +3 more
doaj +1 more source
Exposure to common noxious agents (1), including allergens, pollutants, and micro‐nanoplastics, can cause epithelial barrier damage (2) in our body's protective linings. This may trigger an immune response to our microbiome (3). The epithelial barrier theory explains how this process can lead to chronic noncommunicable diseases (4) affecting organs ...
Can Zeyneloglu +17 more
wiley +1 more source

