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Power characterization of LFSRs
Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99), 2003This paper presents a formal analysis on the power consumption of BIST architectures composed of primitive-polynomial LFSRs connected to a combinational CUT. An exact power characterization of all primitive-polynomial LFSRs has been identified, since interesting invariant properties have been discovered.
M. Brazzarola, FUMMI, Franco
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Proceedings of the 17th IEEE Instrumentation and Measurement Technology Conference [Cat. No. 00CH37066], 2002
This paper presents the preliminary results for a novel mixed-mode scheme to generate test patterns for random pattern resistant faults. It is based on a programmable method in contrast to the hardware implementation used so far. It not only guarantees the full test coverage in the combinational stuck-at faults, but also can be extended to the ...
D. Kay, S. Mourad
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This paper presents the preliminary results for a novel mixed-mode scheme to generate test patterns for random pattern resistant faults. It is based on a programmable method in contrast to the hardware implementation used so far. It not only guarantees the full test coverage in the combinational stuck-at faults, but also can be extended to the ...
D. Kay, S. Mourad
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Comparison of binary and LFSR counters and efficient LFSR decoding algorithm
2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011This paper provides a direct comparison between a fast binary counter, built using a hierarchical Manchester carry chain, and a counter built using a linear feedback shift register (LFSR). The comparison is focused on speed, power and area consumption. We demonstrate the use of LFSRs as an alternative to conventional binary event counters.
Avinash Ajane +3 more
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Proceedings 10th Asian Test Symposium, 2002
Develops a low-power multiphase clock generator, employ static demultiplexers and proposes a hybrid design to reduce the power. The power model is based on the weighted transition count (WTC). The internal gates of a latch consume 2 transitions per cycle when the data changes.
null Tsung-Chu Huang, null Kuen-Jong Lee
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Develops a low-power multiphase clock generator, employ static demultiplexers and proposes a hybrid design to reduce the power. The power model is based on the weighted transition count (WTC). The internal gates of a latch consume 2 transitions per cycle when the data changes.
null Tsung-Chu Huang, null Kuen-Jong Lee
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A low power reconfigurable LFSR
2016 18th Mediterranean Electrotechnical Conference (MELECON), 2016Low power has become an essential design imperative in the era of nanotechnology. In this paper, we propose a new design of energy efficient reconfigurable Linear Feedback Shift Registers(LFSRs). The reconfigurable LFSR design allows an increase in the randomness at the output.
Lama Shaer +4 more
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Parallel computation of LFSR signatures
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS), 2002Off-line determination of signatures (both good circuit and faulty circuits) for built-in self-test applications is a compute-intensive process that involves cycle-by-cycle simulation of the signature analyzer. In this paper, we present a parallel algorithm that can speed up the computation of (single input and multiple input) LFSR signatures by almost
B. Narendran, M. Franklin, K.K. Saluja
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2020 6th International Conference on Advanced Computing and Communication Systems (ICACCS), 2020
A new design of the Linear-feedback shift register (LFSR) using the conditional discharge flip-flop (CDFF) and the Gate-Diffusion-Input (GDI) technique is proposed. This method results in efficient result parameters such as low power, reduced area and minimum usage of transistor than conventional techniques.
S. Kiruthiga +3 more
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A new design of the Linear-feedback shift register (LFSR) using the conditional discharge flip-flop (CDFF) and the Gate-Diffusion-Input (GDI) technique is proposed. This method results in efficient result parameters such as low power, reduced area and minimum usage of transistor than conventional techniques.
S. Kiruthiga +3 more
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2010 10th IEEE International Conference on Computer and Information Technology, 2010
This paper scrutinizes the structure of jump-controlled LFSRs for resistance against generalized correlation attack based upon Constrained Levenshtein Distance(CLD) measure. It proves that for a given number of cipher text bits, CLD computation is independent of Jump index.
Mujahid Mohsin +2 more
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This paper scrutinizes the structure of jump-controlled LFSRs for resistance against generalized correlation attack based upon Constrained Levenshtein Distance(CLD) measure. It proves that for a given number of cipher text bits, CLD computation is independent of Jump index.
Mujahid Mohsin +2 more
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