Results 141 to 150 of about 653 (181)
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Parallel computation of LFSR signatures
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS), 2002Off-line determination of signatures (both good circuit and faulty circuits) for built-in self-test applications is a compute-intensive process that involves cycle-by-cycle simulation of the signature analyzer. In this paper, we present a parallel algorithm that can speed up the computation of (single input and multiple input) LFSR signatures by almost
B. Narendran, M. Franklin, K.K. Saluja
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Breaking LFSR Using Genetic Algorithm
2013In this paper it is shown how to find LFSR using genetic algorithm. LSFRs are part of many cryptographic structures and pseudorandom number generators. Applying genetic algorithms to Linear Feedback Shift Registers (LFSR) cryptanalysis is not quite obvious. Genetic algorithms being one of heuristic techniques give approximate solution. The solution
Iwona Polak, Mariusz Boryczka
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LFSR-Based Generation of Multicycle Tests
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016This paper describes a procedure for computing a multicycle test set whose scan-in states are compressed into seeds for a linear-feedback shift register, and whose primary input vectors are held constant during the application of a multicycle test.
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Application of LFSR with NTRU Algorithm
2007The paper deals with stream cipher based on Linear Feedback Shift Registers (LFSR). A scheme is purposed where n-Linear Feedback Shift Registers are used for the encryption and decryption. Both the public key cryptography and the concept of linear feedback shift registers are used in this scheme.
P. R. Suri, Priti Puri
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Efficient Unknown Blocking Using LFSR Reseeding
Proceedings of the Design Automation & Test in Europe Conference, 2006This paper presents an efficient method to block unknown values from entering temporal compactors. The control signals for the blocking logic are generated by an LFSR. The proposed technique minimizes the size of the LFSR by propagating only one fault effect for each fault and balancing the number of specified bits in each control pattern.
Seongmoon Wang +2 more
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Test Data Compression with Partial LFSR-Reseeding
14th Asian Test Symposium (ATS'05), 2005The large amount of test data becomes a serious problem in SOC testing. In this paper, we propose a method to improve the LFSR reseeding based compression scheme. This method rearranges a given set of test data by merging and partitioning test cubes so that they can be decompressed with a fixed-length LFSR.
Yu-Hsuan Fu, Sying-Jyan Wang
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Low Transition LFSR for BIST-Based Applications
14th Asian Test Symposium (ATS'05), 2005This paper presents a low transition test pattern generator, called LT-LFSR, to reduce average and peak power of a circuit during test by reducing the transitions within randomtest pattern and between consecutive patterns. In other words, transitions are reduced in two dimensions, i.e. between consecutive patterns and bits.
Mohammad Tehranipoor +2 more
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A method of LFSR seed generation for hierarchical BIST
2015 10th International Design & Test Symposium (IDT), 2015In built-in self-test (BIST), pseudo-random patterns generated by a linear feedback shift register (LFSR) are applied to a circuit under test as test patterns. Since random pattern resistant faults (RPRFs) exist, reseeding is used to detect them. In general, seeds that when expanded by the LFSR will produce test patterns for detecting RPRFs are used ...
Kosuke Sawaki, Satoshi Ohtake
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CoLPUF : A Novel Configurable LFSR-based PUF
2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2018In this paper, a new configurable LFSR-based PUF is proposed. This proposed design uses the LFSR states to generate different control signals for selecting the response bits from the ring oscillator frequencies. The main advantage of the design is by generating control signal from the LFSR with the given challenge, one can extend the length of the ...
B. Srinivasu +3 more
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A Novel SMT-Based Technique for LFSR Reseeding
2012 25th International Conference on VLSI Design, 2012In order for logic built-in-self-test (LBIST) to achieve coverages comparable with deterministic tests, multiple (and frequently many) seeds are often needed. Unlike previous methods that attempt to chain/compact the number of seeds, we present a novel Satisfiability Modulo Theory (SMT) based technique that can reduce the number of seeds significantly ...
Sarvesh Prabhu +3 more
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