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Design of Covert Communication Waveform Based on Phase Randomization. [PDF]
Zhou W, Wang Z, Shi J, Guo Q.
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Polygenic strategies for host-specific and general virulence of Botrytis cinerea across diverse eudicot hosts. [PDF]
Caseys C, Kliebenstein DJ.
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Quantum Stream Cipher Based on Holevo-Yuen Theory: Part II. [PDF]
Hirota O, Sohma M.
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Power characterization of LFSRs
Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99), 2003This paper presents a formal analysis on the power consumption of BIST architectures composed of primitive-polynomial LFSRs connected to a combinational CUT. An exact power characterization of all primitive-polynomial LFSRs has been identified, since interesting invariant properties have been discovered.
M. Brazzarola, FUMMI, Franco
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Proceedings 10th Asian Test Symposium, 2002
Develops a low-power multiphase clock generator, employ static demultiplexers and proposes a hybrid design to reduce the power. The power model is based on the weighted transition count (WTC). The internal gates of a latch consume 2 transitions per cycle when the data changes.
Tsung-Chu Huang, Kuen-Jong Lee
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Develops a low-power multiphase clock generator, employ static demultiplexers and proposes a hybrid design to reduce the power. The power model is based on the weighted transition count (WTC). The internal gates of a latch consume 2 transitions per cycle when the data changes.
Tsung-Chu Huang, Kuen-Jong Lee
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Comparison of binary and LFSR counters and efficient LFSR decoding algorithm
2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011This paper provides a direct comparison between a fast binary counter, built using a hierarchical Manchester carry chain, and a counter built using a linear feedback shift register (LFSR). The comparison is focused on speed, power and area consumption. We demonstrate the use of LFSRs as an alternative to conventional binary event counters.
Avinash Ajane +3 more
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Proceedings of the 17th IEEE Instrumentation and Measurement Technology Conference [Cat. No. 00CH37066], 2002
This paper presents the preliminary results for a novel mixed-mode scheme to generate test patterns for random pattern resistant faults. It is based on a programmable method in contrast to the hardware implementation used so far. It not only guarantees the full test coverage in the combinational stuck-at faults, but also can be extended to the ...
D. Kay, S. Mourad
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This paper presents the preliminary results for a novel mixed-mode scheme to generate test patterns for random pattern resistant faults. It is based on a programmable method in contrast to the hardware implementation used so far. It not only guarantees the full test coverage in the combinational stuck-at faults, but also can be extended to the ...
D. Kay, S. Mourad
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