Results 71 to 80 of about 8,847,760 (170)

First-Arrival Differential Counting for SPAD Array Design. [PDF]

open access: yesSensors (Basel), 2023
White M   +5 more
europepmc   +1 more source

Matrix: a 15 ps resistive interpolation TDC ASIC based on a novel regular structure

open access: yes
This paper presents a 4-channel TDC ASIC with the following features: 15-ps LSB (9.34 ps after calibration), 10-ps jitter, < 4-ps time resolution, up to 10 MHz of sustained input rate per channel, 45 mW of power consumption and very low area (910×215 μm2)
Fernández, G.   +5 more
core  

A low jitter PLL frequency synthesizer for high resolution TDCs in 65nm CMOS technology

open access: yes, 2015
A PLL has been designed for high frequency clock generation with only 280 fs RMS jitter. The integer N PLL multiplies a 40 MHz reference clock to 2.56 GHz.
Christiansen, Jorgen   +4 more
core  

Towards a Multi-Pixel Photon-to-Digital Converter for Time-Bin Quantum Key Distribution. [PDF]

open access: yesSensors (Basel), 2023
Carrier S   +11 more
europepmc   +1 more source

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