Results 51 to 60 of about 8,847,760 (170)
Towards low-timing jitter photon number-resolved digital silicon photomultipliers
, 2021 An innovative general-purpose Digital Silicon-PhotoMultiplier (dSiPM) with 32 x 32 SPADs, designed in 160 nm BCD technology, is presented. The main goals of this device are to enhance the dynamic range, still keeping the single-photon resolution, and ...
Incoronato, Alfonso +11 more
core +1 more source
A Fast-Lock Variable-Gain TDC-Based N/M-Ratio MDLL Clock Multiplier
, 2023 A variable-gain time-to-digital converter (TDC)-based multiplying delay-locked loop (MDLL) clock multiplier featuring fast-locking and programmable N/M-ratio frequency multiplication capability is presented in this paper.
Chaeyoung Jang, Jongsun Kim
core +1 more source
A fractional-N digital PLL employing a two-track probability-density-shaping ΔΣ modulator and a dithered-threshold TDC is presented. The first technique suppresses spurs arising from quadratic DTC nonlinearity while minimizing the required DTC delay ...
Rossoni, Michele +8 more
core +1 more source
A SPAD-based 3D imager with in-pixel TDC for 145ps-accuracy ToF measuremen [PDF]
, 2015 Comunicación presentada al Image Sensors and Imaging Systems celebrado en San Francsico del 9 al 10 de Febrero de 2015The design and measurements of a CMOS 64 × 64 Single-Photon Avalanche-Diode (SPAD) array with in-pixel Time-to-Digital Converter (TDC ...
Á. Rodríguez-Vázquez +7 more
core +1 more source
A Low-Latency, Low-Jitter Retimer Circuit for PCIe 6.0
, 2023 As the PCIe 6.0 specification places higher requirements on signal integrity and transmission latency, it becomes especially important to improve signal transmission performance at the physical layer of the transceiver interface.
Geng Zhang +4 more
core +1 more source
RO-Based TDC Design with Configurable Resolution and Power for SPAD-Based TCSPC LiDAR Applications [PDF]
, 2022 Single-photon avalanche diodes (SPAD) are used to measure time-of-flight (ToF) using CMOS time-to-digital Converters (TDCs) for compact, low-cost, and highly integrated three-dimensional (3D) sensing.
Arvani, Foad
core
On-chip accumulated jitter measurement for phase-locked loops
, 2005 [[abstract]]A time-to-digital converter (TDC) circuit is presented to measure the worst-case accumulated jitters over N periods of clock produced by the PLL.
Tsin-Yuan Chang +2 more
core +1 more source
A high-speed optical star network using TDMA and all-optical demultiplexing techniques [PDF]
, 1996 The authors demonstrate the use of time-division multiplexing (TDM) to realize a high capacity optical star network. The fundamental element of the demonstration network is a 10 ps, wavelength tunable, low jitter, pulse source. Electrical data is encoded
Remi Boittin +8 more
core +2 more sources
A TDC-less all-digital phase locked loop for medical implant applications
, 2019 A TDC-less, ultra-low area and low power all-digital phase locked loop (ADPLL) has been designed for use in biomedical implant transceivers. The proposed ADPLL eliminates the use of LC oscillator and time-to-digital converter (TDC) for achieving a low ...
Siek, Liter +1 more
core +1 more source