Results 61 to 70 of about 8,847,760 (170)

A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with-106dBc/Hz In-band noise using time amplifier based TDC

, 2014
A digital fractional-N PLL that employs a time amplifier based TDC and a truly fractional divider to achieve low in-band noise with a wide bandwidth of 3MHz is presented.
Anand, Tejasvi, Elkholy, Ahmed, Elshazly, Amr, Hanumolu, Pavan Kumar, Choi, Woo Seok   +4 more
core   +1 more source

Design and Characterization of a High-Precision High-Stability Pulse-Shrinking TDC

IEEE Transactions on Instrumentation and Measurement
This work presents a high-precision, low-dead-time pulse-shrinking time-to-digital converter (TDC) implemented on an AMD Versal Prime VM1402 field-programmable gate array (FPGA).
Yu-Cheng Zhang, Kai Chen, Hongtao Li, Yan Dai   +3 more
semanticscholar   +1 more source

Techniques for low jitter clock multiplication [PDF]

, 2008
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p.
Helal, Belal M., 1971-
core  

A 400 MHz 0.934ps rms Jitter Multiplying Delay Lock Loop in 90-nm CMOS Process

, 2011
A multiplying delay-locked loop (MDLL) is adopted for low-jitter clock generation. This architecture overcomes the drawback of phase-locked loops (PLL) such as jitter accumulation, and maintain the advantage of a PLL for multirate frequency ...
施鴻源; 陳秋榜
core  

A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC

, 2014
The introduction of inductorless frequency synthesizers into standardized wireless systems still requires a high level of innovation in order to achieve the stringent requirements of low noise and low power consumption.
Andrea L. Lacaita, LEVANTINO, SALVATORE, Salvatore Levantino, LACAITA, ANDREA LEONARDO, Giovanni Marzin, Andrea Fenaroli, MARUCCI, GIOVANNI, SAMORI, CARLO, FENAROLI, ANDREA, Giovanni Marucci, Carlo Samori   +10 more
core   +1 more source

A new delta-sigma time-to-digital converter for low-jitter digital PLLs

, 2020
LAUREA MAGISTRALEIl repentino aumento nella velocità di trasmissione di dati nelle comunicazioni wireless 5G, ha portato all’utilizzo di onde millimetriche e modulazioni numeriche di ampiezza in quadratura (QAM) di ordine sempre più elevato, che hanno ...
SHEHATA, ABANOB
core  

An Observer-Data-Path Decoupled Time-Domain ADC with Three-Stage Digital Background Calibration in 28 nm CMOS. [PDF]

Micromachines (Basel)
Qin C, Liu B, Wang R, Li L, Zhang C.
europepmc   +1 more source

Performance of detector modules designed for the NeuroSphere brain PET system. [PDF]

Med Phys
Allen MS, Byars L, Rauscher L, Scipioni M, Puryear M, Judenhofer M, Hen O, Schmidt FP, Catana C.   +8 more
europepmc   +1 more source

Developing the Readout Electronics for a Custom 64 × 64 SPAD Array: From Single-Board Prototyping to FPGA Implementation Toward Stellar Intensity Interferometry. [PDF]

Sensors (Basel)
Quintana Á, González-de-Rivera G, López-Buedo S, Prada F.   +3 more
europepmc   +1 more source

A 2-GS/s 35.9-fJ/conv.-step Voltage-Time Hybrid Pipelined ADC with Digital Background Calibration in 28-nm CMOS. [PDF]

Micromachines (Basel)
Chang Y, Zhang C, Yang Y, Zhang C, Liu M, Chen D, Yang Y.   +6 more
europepmc   +1 more source