Results 251 to 260 of about 136,493 (299)

Energy recovery for low-power CMOS

Proceedings Sixteenth Conference on Advanced Research in VLSI, 2002
Energy recovery, as a means to trade off power dissipation for performance in CMOS logic circuits, is analyzed and investigated. A mathematical model is presented to estimate the efficiency for two energy-recovery approaches under varying conditions of voltage swing, transition time, and MOS device parameters. This model can be directly compared to the
W.C. Athas, N. Tzartzanis
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Low power CMOS bandgap reference circuit

2014 IEEE Student Conference on Research and Development, 2014
Bandgap Reference (BGR) circuit is to yield a precise and accurate dc voltage which has minimum variation over an external influence. The objective of this BGR paperwork lies on using two different temperature-compensation techniques which are based on the resistor-subdivision method and resistor-less method on same BGR circuit structure.
Koh, S. K., Lee, Lini
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Low-power Single-chip CMOS Potentiostat

Proceedings of the International Solid-State Sensors and Actuators Conference - TRANSDUCERS '95, 2005
A monolithic potentiostat for chemical and biochemical sensors is presented. It allows measurements that use two- or three-clectrode-configurations in amperometric and voltammetric mode. The amplification part converts the electrode current with an input range from +/-0.1 InA up to +/-0.5/splmu/A.
R.G. Kakerow, H. Kappert, E. Spiegel, Y. Manoli   +3 more
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Low power Gb/s CMOS interfaces

Digest of Technical Papers., Symposium on VLSI Circuits., 2002
For high-speed digital systems, it is important to develop point-to-point Gb/s interfaces that consume low power during low-transition-rate operation. This paper presents two novel Gb/s CMOS interfaces. One uses an active-pull-up (APU) technique to raise the maximum transmission speed.
Y. Ohtomo, M. Nogawa
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A 1GHz low power CMOS LNA

2007 International Conference on Microwave and Millimeter Wave Technology, 2007
A 1.8 V 0.18 um CMOS LNA for GPS applications has been designed and under the supply voltage, the fully differential LNA has been simulated. It provides a series of good results in Noise figure, Linearity and Power dissipation. The LNA achieves a voltage gain of 24 dB, Noise figure of 1.7 dB and Power dissipation of 9 mW. Besides, the input third-order
null Zhang-Jie, null Hong-Qi
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Designing low-power digital CMOS

Electronics & Communication Engineering Journal, 1994
The increasing levels of circuit integration are leading to the implementation of highly sophisticated algorithms. Many of the commercial application areas have a requirement for portability, which leads to the need for low-power design. This paper considers the issues and design solutions for complex low-power digital CMOS IC design.
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Low power CMOS wideband receiver design

Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004., 2005
A low power CMOS receiver for ultra-wideband (UWB) wireless applications is presented. The low-noise amplifier (LNA) building block employing stagger tuning technique consists of two common-source stages with different resonance frequencies to achieve low power consumption and wide operating bandwidth.
null Chao-Chun Sung, null Mei-Fen Chou, null Chang-Cbing Wu, null Cbe-Sheng Chen, null Kuei-Ann Wen, null Chun-Yen Chang   +5 more
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Low-power beyond-CMOS devices

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014
Low-power beyond-CMOS devices based on charge and non-charge state variables are reviewed with brief assessment of their advantages and challenges. Promising applications of these devices may depend on novel design and architecture solutions utilizing their unique properties, e.g., nonvolatility, efficient logic design, etc.
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"Low power, variable supply CMOS comparator "

Proceedings of the IEEE 12th Signal Processing and Communications Applications Conference, 2004., 2004
The design of a variable supply CMOS comparator using AMS/sup /spl reg// 0.35 /spl mu/m technology is presented. The comparator is optimized for a DC-DC converter used in low power portable communication applications. The designed comparator can operate well between 1 V and 3 V supply voltages.
M. Parlak, Y. Gurbuz
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A low-power CMOS analog multiplier

IEEE Transactions on Circuits and Systems II: Express Briefs, 2006
A multiplier is an important component for many analog applications. This paper presents a low power CMOS analog multiplier with performance analysis and design considerations. Experiments with SPICE simulation and results from chip testing show that this new structure has extremely low power consumption with comparable linearity and noise performance,
null Chunhong Chen, null Zheng Li
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