Results 161 to 170 of about 110,447 (234)

ReD-LUT

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
In this paper, we propose a reconfigurable processing-in-DRAM architecture named ReD-LUT leveraging the high density of commodity main memory to enable a flexible, general-purpose, and massively parallel computation.
Ranyang Zhou, Arman Roohi, Durga Misra, Shaahin Angizi   +3 more
openaire   +2 more sources

LUT Input Reordering to Reduce Aging Impact on FPGA LUTs

IEEE Transactions on Computers, 2020
In this article, we propose a fine-grained FPGA aging mitigation method. Our method focuses on Look Up Tables (LUTs) on which Boolean functions are mapped. Based on our observations, for any configuration, even if it is carefully selected, a number of LUT transistors experience severe stress rates. Therefore, an algorithm is presented to select several
Mohammad Ebrahimi, Rezgar Sadeghi, Zainalabedin Navabi   +2 more
openaire   +2 more sources

Adaptive LUT - Decoder LUT for FPGAs

2023 Seminar on Microelectronics, Dielectrics and Plasmas (MDP), 2023
Sergey F Tyurin
exaly   +2 more sources

Self-timed LUT Layout Simulation

IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering, 2020
The paper proposes Self-timed LUT for FPGAs. The following options are considered: Self-timed LUT with dual channel, spacer circuit and indicator; DC- Self-timed LUT; DNF - Self-timed LUT.
A. Y. Skornyakova, R. Vikhorev
exaly   +2 more sources

On Custom LUT-based Obfuscation

Proceedings of the 2019 Great Lakes Symposium on VLSI, 2019
Logic obfuscation yields hardware security against various threats, such as Intellectual Property (IP) piracy and reverse engineering. Evolving Boolean satisfiability (SAT) attacks have challenged the hardware security assurance rendered by various obfuscation methods.
Gaurav Kolhe, Sai Manoj P. D., Setareh Rafatirad, Hamid Mahmoodi, Avesta Sasan, Houman Homayoun   +5 more
openaire   +2 more sources

Efficient LUT Design Methodologies of Transformation between RGB and HSV for HSV Based Image Enhancements

Journal of Electrical Engineering and Technology
Jaehee You
exaly   +2 more sources

An Accurate VSI Nonlinearity Modeling and Compensation Method Accounting for DC-Link Voltage Variation Based on LUT

IEEE transactions on industrial electronics (1982. Print), 2022
The nonlinearity of the voltage source inverter (VSI) leads to the error between output voltage and reference voltage, and causes the phase current harmonics.
Chaoyi Shang, Ming Yang, Jiang Long, Dianguo Xu, Jun Zhang, J. Zhang   +5 more
semanticscholar   +1 more source

NN-LUT: Neural Approximation of Non-Linear Operations for Efficient Transformer Inference

Design Automation Conference, 2021
Non-linear operations such as GELU, Layer normalization, and Softmax are essential yet costly building blocks of Transformer models. Several prior works simplified these operations with look-up tables or integer computations, but such approximations ...
Joonsang Yu, Junki Park, Seongmin Park, Minsoo Kim, Sihwa Lee, Dong Hyun Lee, Jungwook Choi   +6 more
semanticscholar   +1 more source