Results 1 to 10 of about 21,469 (110)
Reducing LUT Count for FPGA-Based Mealy FSMs
Applied Sciences (Switzerland), 2020 Very often, digital systems include sequential blocks which can be represented using a model of Mealy finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and power
Larysa Titarenko +2 more
exaly +4 more sources
Improving Hardware in LUT-Based Mealy FSMs
Applied Sciences (Switzerland), 2022 The main contribution of this paper is a novel design method reducing the number of look-up table (LUT) elements in the circuits of three-block Mealy finite-state machines (FSMs). The proposed method is based on using codes of collections of outputs (COs)
Larysa Titarenko +2 more
exaly +4 more sources
Improving characteristics of LUT-based Mealy FSMs [PDF]
International Journal of Applied Mathematics and Computer Science, 2020 Practically, any digital system includes sequential blocks represented using a model of finite state machine (FSM). It is very important to improve such FSM characteristics as the number of logic elements used, operating frequency and consumed energy ...
Barkalov Alexander +2 more
doaj +2 more sources
Improving the Spatial Characteristics of Three-Level LUT-Based Mealy FSM Circuits
Electronics (Switzerland), 2023 The main purpose of the method proposed in this article is to reduce the number of look-up-table (LUT) elements in logic circuits of sequential devices. The devices are represented by models of Mealy finite state machines (FSMs). Thesee are so-called MPY
Larysa Titarenko +2 more
exaly +2 more sources
Encoding of Terms in EMB-Based Mealy FSMs
Applied Sciences, 2020 A method is proposed targeting implementation of FPGA-based Mealy finite state machines. The main goal of the method is a reduction for the number of look-up table (LUT) elements and their levels in FSM logic circuits.
Alexander Barkalov +3 more
doaj +2 more sources
Improving Characteristics of LUT-Based Mealy FSMs with Twofold State Assignment
Electronics (Switzerland), 2021 Practically, any digital system includes sequential blocks. This article is devoted to a case when sequential blocks are represented by models of Mealy finite state machines (FSMs).
Larysa Titarenko +2 more
exaly +2 more sources
Improving the Characteristics of Multi-Level LUT-Based Mealy FSMs
Electronics (Switzerland), 2020 Contemporary digital systems include many varying sequential blocks. In the article, we discuss a case when Mealy finite state machines (FSMs) describe the behavior of sequential blocks. In many cases, the performance is the most important characteristic
Larysa Titarenko +2 more
exaly +2 more sources
Improving Temporal Characteristics of Mealy FSM with Composite State Codes
Electronics (Switzerland)In this paper, we proposed a new state assignment method focusing on Mealy finite state machines (FSMs). The method makes it possible to improve the temporal characteristics of the circuits of FSMs, the internal states of which are encoded by the ...
Larysa Titarenko +2 more
exaly +2 more sources
Using a Double-Core Structure to Reduce the LUT Count in FPGA-Based Mealy FSMs
Electronics (Switzerland), 2022 A method is proposed which aims at reducing the numbers of look-up table (LUT) elements in logic circuits of Mealy finite state machines (FSMs). The FSMs with twofold state assignment are discussed.
Larysa Titarenko +2 more
exaly +2 more sources
Reducing Hardware in LUT-Based Mealy FSMs with Encoded Collections of Outputs
Electronics (Switzerland), 2022 A method is proposed that is focused on reducing the chip area occupied by logic elements creating the circuit of Mealy finite state machines (FSMs). The proposed method is aimed at FSM circuits implemented with internal resources of field-programmable ...
Larysa Titarenko +2 more
exaly +2 more sources