Results 11 to 20 of about 22,185 (127)
Reducing LUT Count for FPGA-Based Mealy FSMs [PDF]
Applied Sciences (Switzerland), 2020 Very often, digital systems include sequential blocks which can be represented using a model of Mealy finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and power
Larysa Titarenko +2 more
exaly +5 more sources
Improving Hardware in LUT-Based Mealy FSMs
Applied Sciences (Switzerland), 2022 The main contribution of this paper is a novel design method reducing the number of look-up table (LUT) elements in the circuits of three-block Mealy finite-state machines (FSMs). The proposed method is based on using codes of collections of outputs (COs)
Larysa Titarenko +2 more
exaly +5 more sources
Improving the LUT Count for Mealy FSMS with Transformation of Output Collections [PDF]
International Journal of Applied Mathematics and Computer Science, 2022 A method is proposed which aims at reducing the number of LUTs in the circuits of FPGA-based Mealy finite state machines (FSMs) with transformation of collections of outputs into state codes.
Barkalov Alexander +2 more
doaj +4 more sources
Improving LUT count of FPGA-based sequential blocks [PDF]
Bulletin of the Polish Academy of Sciences: Technical Sciences, 2021 Very often, a digital system includes sequential blocks which can be represented using a model of the finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and ...
Alexander Barkalov +3 more
doaj +3 more sources
Separation of Input Variables for Optimization of the Mealy FSM Circuit
Кібернетика та комп'ютерні технології, 2023 Introduction. One of the most important blocks of almost any digital system is the control device (CU), since the characteristics of the CU largely determine the characteristics of the system as a whole.
Alexandr Barkalov +4 more
doaj +2 more sources
Using a Double-Core Structure to Reduce the LUT Count in FPGA-Based Mealy FSMs
Electronics, 2022 A method is proposed which aims at reducing the numbers of look-up table (LUT) elements in logic circuits of Mealy finite state machines (FSMs). The FSMs with twofold state assignment are discussed. The reduction is achieved due to using two cores of LUTs for generating partial Boolean functions. One core is based on maximum binary state codes.
Alexander Barkalov +2 more
openaire +2 more sources
Improving Characteristics of FSMs With Mixed Codes of Outputs
IEEE Access, 2022 Practically, any digital system includes sequential blocks. This paper considers a case when LUT-based sequential blocks are represented by Mealy finite state machines (FSMs).
Alexander Barkalov +3 more
doaj +1 more source
Improving Characteristics of LUT-Based Sequential Blocks for Cyber-Physical Systems
Energies, 2022 A method is proposed for optimizing circuits of sequential devices which are used in cyber-physical systems (CPSs) implemented using field programmable gate arrays (FPGAs).
Alexander Barkalov +2 more
doaj +1 more source
Structural models of Mealy finite state machines detecting faults in control systems
Радіоелектронні і комп'ютерні системи, 2023 The subject matter of this article is a control system for unmanned aerial vehicles (UAVs) whose mathematical model is a finite state machine (FSM). The goal is to develop FSM structural models that enable (1) detection of multiple faults of FSM elements
Valery Salauyou
doaj +1 more source
Applied Sciences, 2023 This work proposes a method for hardware reduction in circuits of Mealy finite state machines (FSMs). The circuits are implemented as networks of interconnected look-up table (LUT) elements.
Alexander Barkalov +3 more
doaj +1 more source