Results 1 to 10 of about 562,616 (186)
Reducing LUT Count for FPGA-Based Mealy FSMs [PDF]
Applied Sciences, 2020 Very often, digital systems include sequential blocks which can be represented using a model of Mealy finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and power
Alexander Barkalov +2 more
doaj +4 more sources
Improving LUT count of FPGA-based sequential blocks [PDF]
Bulletin of the Polish Academy of Sciences: Technical Sciences, 2021 Very often, a digital system includes sequential blocks which can be represented using a model of the finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and ...
Alexander Barkalov +3 more
doaj +2 more sources
Improving the LUT Count for Mealy FSMS with Transformation of Output Collections
International Journal of Applied Mathematics and Computer Science, 2022 A method is proposed which aims at reducing the number of LUTs in the circuits of FPGA-based Mealy finite state machines (FSMs) with transformation of collections of outputs into state codes.
Barkalov Alexander +2 more
doaj +3 more sources
Improving Characteristics of LUT-Based Sequential Blocks for Cyber-Physical Systems
Energies, 2022 A method is proposed for optimizing circuits of sequential devices which are used in cyber-physical systems (CPSs) implemented using field programmable gate arrays (FPGAs).
Alexander Barkalov +2 more
doaj +3 more sources
Improving Hardware in LUT-Based Mealy FSMs
Applied Sciences, 2022 The main contribution of this paper is a novel design method reducing the number of look-up table (LUT) elements in the circuits of three-block Mealy finite-state machines (FSMs). The proposed method is based on using codes of collections of outputs (COs)
Alexander Barkalov +2 more
doaj +3 more sources
Using a Double-Core Structure to Reduce the LUT Count in FPGA-Based Mealy FSMs
Electronics (Switzerland), 2022 A method is proposed which aims at reducing the numbers of look-up table (LUT) elements in logic circuits of Mealy finite state machines (FSMs). The FSMs with twofold state assignment are discussed. The reduction is achieved due to using two cores of LUTs for generating partial Boolean functions. One core is based on maximum binary state codes.
Larysa Titarenko +2 more
exaly +2 more sources
Improving Characteristics of FSMs With Mixed Codes of Outputs
IEEE Access, 2022 Practically, any digital system includes sequential blocks. This paper considers a case when LUT-based sequential blocks are represented by Mealy finite state machines (FSMs).
Alexander Barkalov +3 more
doaj +1 more source
Peripheral Lymphocyte Count, Free/Total PSA Ratio, LUTS Predict The Severity of Prostatic Inflammation in BPH Patients [PDF]
, 2021 Abstract Objective To study the correlation between peripheral blood lymphocytes, f/t PSA and LUTS symptoms, and prostatic inflammation in BPH patients.Materials and Methods From May 2020 to October 2020, 120 patients (aged 56-85 years) with BPH undergoing elective transurethral resection of the prostate (TURP) were selected.
Shun Wan +7 more
openaire +1 more source
LUT Based Generalized Parallel Counters for State-of-art FPGAs [PDF]
Electronics, 2017 Generalized Parallel Counters (GPCs) are frequently used in constructing high speed compressor trees. Previous work has focused on achieving efficient mapping of GPCs on FPGAs by using a combination of general Look-up table (LUT) fabric and specialized ...
Burhan Khurshid
doaj +1 more source
IEEE Access, 2022 Training a CNN involves computationally intense optimization algorithms to fit the network using a training dataset, to update the network weight for inferencing and then pattern classification.
Nagaraj Lakshmana Prabhu +1 more
doaj +1 more source