Results 21 to 30 of about 562,616 (186)
Sähkönjakeluverkkoliiketoiminnan sääntely ja kehittäminen [PDF]
Tässä raportissa tarkastellaan sähkönjakeluverkkoliiketoiminnan valvontaan liittyvän sääntelyn nykytilaa, tavoitteita, haasteita ja sääntelyn kautta saavutettuja tuloksia.
Haakana, Juha +2 more
core +1 more source
A new architecture and design method are proposed for field-programmable gate array (FPGA)-based Moore finite state machines (FSMs). The proposed architecture includes a core based on functional decomposition, a core based on twofold state assignment ...
Alexander Barkalov +2 more
doaj +1 more source
Efficient Realization of BCD Multipliers Using FPGAs
In this paper, a novel BCD multiplier approach is proposed. The main highlight of the proposed architecture is the generation of the partial products and parallel binary operations based on 2-digit columns.
Shuli Gao +3 more
doaj +1 more source
Bothnian Bay Hydrogen Valley – Research report [PDF]
This report is part of a commissioned research, ordered jointly by Fortum and St1. The re-search was carried out by LUT University between 1.4.2021 – 31.10.2021.
Laari, Arto +10 more
core +1 more source
GC cells enhance glutamine accumulation by upregulating SLC1A5 expression. This upregulation not only boosts GC cell proliferation, but also outcompetes CD8+ T cells for glutamine and suppresses their antitumor immunity. Mechanistically, METTL7A deficiency in GC induces SLC1A5 overexpression via an m6A‐dependent pathway and N‐glycosylation ...
Mingjun Sun +16 more
wiley +1 more source
Hiilineutraali Yrityspuisto (CNBP) -hankkeen loppuraportti [PDF]
Tämä on EAKR-hankkeen ”Hiilineutraali Yrityspuisto (CNBP)” loppuraportti, jossa keskitymme raportoimaan LUT-Yliopiston hankkeessa tekemät laskelmat, tutkimus sekä tuotetut tulokset.
Mustonen, Helka +4 more
core +1 more source
Probabilistic Computing via Gate‐Tunable Random Telegraph Noise
Intrinsic random telegraph noise in metal–oxide–semiconductor field‐effect transistors is harnessed to create gate‐tunable probabilistic bits. By modulating carrier‐trapping dynamics, the device produces stochastic binary outputs with a continuous bias‐to‐probability transfer.
Gyungwon Yun +8 more
wiley +1 more source
Reducing LUT Counts in Moore FSMs with Twofold State Assignment
In this paper, we propose a new synthesis method for LUT-based Moore finite state machines (FSMs) with twofold state assignment (TSA). The method introduces an additional core of partial input memory functions (IMFs), resulting in an architecture with two IMF cores.
Alexander Barkalov +2 more
openaire +1 more source
Capacitive, charge‐domain compute‐in‐memory (CIM) stores weights as capacitance,eliminating DC sneak paths and IR‐drop, yielding near‐zero standbypower. In this perspective, we present a device to systems level performance analysis of most promising architectures and predict apathway for upscaling capacitive CIM for sustainable edge computing ...
Kapil Bhardwaj +2 more
wiley +1 more source
Hardware Reduction for FSMs With Extended State Codes
A method is proposed for reducing chip area occupied by logic circuits of FPGA-based Mealy finite state machines (FSMs). The proposed method aims at optimization of FSM circuits implemented with look-up table (LUT) elements of FPGA chip.
Alexander Barkalov +3 more
doaj +1 more source

