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Malicious LUT: A stealthy FPGA Trojan injected and triggered by the design flow
2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2016C. Krieg, Clifford Wolf, A. Jantsch
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FPGA Implementation of High Quality Random Number Generator Using LUT Based Shift Registers
Procedia Technology, 2016exaly
ELMap: Area-Driven LUT Mapping with $k$-LUT Network Exact Synthesis
2025 Design, Automation & Test in Europe Conference (DATE)Hongyang Pan +4 more
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BILATERAL FILTER WITH LUT AVOIDING UNNECESSARY MULTIPLICATION AND MINIMIZING THE LUT
2020STRÖM JACOB +3 more
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