Results 21 to 30 of about 1,071,906 (249)
Improving Hardware in LUT-Based Mealy FSMs
Applied Sciences, 2022 The main contribution of this paper is a novel design method reducing the number of look-up table (LUT) elements in the circuits of three-block Mealy finite-state machines (FSMs). The proposed method is based on using codes of collections of outputs (COs)
Alexander Barkalov +2 more
doaj +1 more source
Verkostoitumisella voimaa 3D-tulostukseen (VERKOTA) -project report [PDF]
, 2023 The project strength to industrial 3D printing via networking and research, VERKOTA (Verkostoitumisella voimaa 3D-tulostukseen) is funded by the European Regional Development Fund (ERDF).
Afkhami, Shahriar +2 more
core +1 more source
Hybrid product term and LUT based architectures using embedded memory blocks [PDF]
Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, 1999 The Embedded System Block (ESB) of the APEX20K programmable logic device family from Altera Corporation includes the capability of implementing product term macrocells in addition to flexibly configurable ROM and dual port RAM. In product term mode, each ESB has 16 macrocells built out of 32 product terms with 32 literal inputs.
Frank Heile, Andrew Leaver
openaire +2 more sources
Gender Classification by LUT Based Boosting of Overlapping Block Patterns [PDF]
, 2015 The paper addresses the problem of gender classification from face images. For feature extraction, we propose discrete Overlapping Block Patterns (OBP), which capture the characteristic structure from the image at various scales. Using integral images, these features can be computed in constant time. The feature extraction at multiple scales results in
Rakesh Mehta +2 more
openaire +1 more source
Improving Characteristics of LUT-Based Sequential Blocks for Cyber-Physical Systems
Energies, 2022 A method is proposed for optimizing circuits of sequential devices which are used in cyber-physical systems (CPSs) implemented using field programmable gate arrays (FPGAs). The optimizing hardware is a very important problem connected with implementing digital parts of CPSs.
Alexander Barkalov +2 more
openaire +2 more sources
LieteKierto-hankkeen loppuraportti [PDF]
, 2022 LieteKierto-hankkeessa selvitettiin yhdyskuntalietteen käsittelyketjuja, niihin liittyviä toimijoita, kustannuksia, liiketoimintamalleja, teknisiä rajoitteita ja paikallisia tekijöitä, jotka vaikuttavat lietteen käsittelyketjun valintaan.
Kinnarinen, Teemu
core +1 more source
Mining, 2021 The eastern Lut block of Iran has a high potential for porphyry copper mineralization due to the subduction tectonic regime. It is located in an inaccessible region and has harsh arid conditions for traditional mineral exploration campaigns.
Vahid Khosravi +4 more
doaj +1 more source
Journal of Economic Geology, 2023 Balazard prospecting area is located in eastern Iran, about 120 km south-west of Nehbandan in the Central part of Lut Block. This area consists of exposed Eocene volcanic rocks, intruded by several diorite and monzodiorite dykes and stocks.
Roohollah Miri Bydokhti +3 more
doaj +1 more source
Tectonic analysis of curved northern border of the Sistan zone with the Lut Block, north of Birjand [PDF]
علوم زمین خوارزمی, 2023 The curved fold-thrust belt of North Birjand contains some outcrops of Upper Paleozoic to Cenozoic sequences that have undergone several stages of deformation. Thrusting, large-scale parallel and radial folds, penetrative shear cleavage, tectonic klippes,
shahriar keshtgar +4 more
doaj
Area–Oriented Technology Mapping for LUT–Based Logic Blocks
International Journal of Applied Mathematics and Computer Science, 2017 Abstract One of the main aspects of logic synthesis dedicated to FPGA is the problem of technology mapping, which is directly associated with the logic decomposition technique. This paper focuses on using configurable properties of CLBs in the process of logic decomposition and technology mapping.
Marcin Kubica 0002, Dariusz Kania
openaire +2 more sources