Results 121 to 130 of about 654,361 (135)
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Reducing LUT Count in FSMs With Transformation of Objects.
Alexander Barkalov +2 moreexaly +2 more sources
Designing efficient input interconnect blocks for LUT clusters using counting and entropy
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays, 2007In a cluster-based FPGA, the interconnect from external routing tracks and cluster feedbacks to the LUT inputs consumes significant area, and no consensus has emerged among different implementations (e.g., 1-level or 2-level). In this paper, we model this interconnect as a unified input interconnect block (IIB).
Wenyi Feng, Sinan Kaptanoglu
openaire +2 more sources
Synchronous up/down binary counter for LUT FPGAs with counting frequency independent of counter size
Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays - FPGA '97, 1997This paper presents the design of a fast binary counter for LUT FPGAs. The counter has a cycle time independent of the counter size. The key aspects of the design are described and applied to a 64-bit synchronous binary counter implemented in a XC4010 FPGA chip. Experimental results show that the counter can scale up to hundreds of bits while keeping a
Alexandre F. Tenca, Milos D. Ercegovac
openaire +1 more source
Approximate synthesis for LUT count reduction via probabilistic error propagation
it - Information TechnologyAbstract Approximate computing is an fast developing area for resource-efficient and fast designs that trades off computational accuracy with non-functional aspects such as delay, energy requirements or area. It can be used for applications where it is acceptable to compute inaccurate results such as image processing.
Thomas Schlögl, Oliver Keszöcze
openaire +1 more source
Using Boolean Algebra to Minimize the LUT Count for FPGA Implementation of BCD Adders
International Journal of Circuit Theory and ApplicationsABSTRACT In this paper, the binary coded decimal (BCD) adder is efficiently mapped to FPGA resources to minimize the LUT consumption for different bit‐widths. Every FPGA slice contains a fast carry chain block CARRY4 which is used to add two BCD digits along with an input carry. The decimal adjustment after the addition is efficiently
openaire +1 more source
Improving Characteristics of LUT-Based Three-Block Mealy FSMs’ Circuits
Electronics, 2022Larysa Titarenko +2 more
exaly
A New Method of Predicting US and State-Level Cancer Mortality Counts for the Current Calendar Year
Ca-A Cancer Journal for Clinicians, 2004Ahmedin Jemal +2 more
exaly
Look-Up Table (LUT) Method for Inverse Halftoning
IEEE Transactions on Image Processing, 2001Palghat Vaidyanathan, P P Vaidyanathan
exaly