Lut count - Open Access .click

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022
Modern digital systems can be viewed as compositions of combinational and sequential blocks. In the article, we discuss a case when sequential blocks are represented using a model of Mealy finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and power consumption.
Larysa Titarenko, Oleksandr Barkalov, Kamil Mielcarek +2 more
exaly +2 more sources

Reducing LUT count in FSMs with transformation of objects.

Alexander Barkalov, Larysa Titarenko, Kazimierz Krzywicki +2 more
exaly +2 more sources

Designing efficient input interconnect blocks for LUT clusters using counting and entropy

Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays, 2007
In a cluster-based FPGA, the interconnect from external routing tracks and cluster feedbacks to the LUT inputs consumes significant area, and no consensus has emerged among different implementations (e.g., 1-level or 2-level). In this paper, we model this interconnect as a unified input interconnect block (IIB).
Wenyi Feng, Sinan Kaptanoglu
openaire +2 more sources

Synchronous up/down binary counter for LUT FPGAs with counting frequency independent of counter size

Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays - FPGA '97, 1997
This paper presents the design of a fast binary counter for LUT FPGAs. The counter has a cycle time independent of the counter size. The key aspects of the design are described and applied to a 64-bit synchronous binary counter implemented in a XC4010 FPGA chip. Experimental results show that the counter can scale up to hundreds of bits while keeping a
Alexandre F. Tenca, Milos D. Ercegovac
openaire +1 more source

fpga
mealy fsm
lut

synthesis
structural decomposition
extended state codes

3. good health
7. clean energy
replacement of inputs