Results 281 to 290 of about 381,026 (309)
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Efficient String Sorting on Multi - and Many-Core Architectures
2014 IEEE International Congress on Big Data, 2014This paper addresses the issue of efficient sorting of strings on multi-and many-core processors. We propose CPU and GPU implementations of the most-significant digit radix sort algorithm using different parallelization strategies on various stages of the execution to achieve good workload balance and optimal use of system resources.
Aleksandr Drozd +2 more
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Gregarious Data Re-structuring in a Many Core Architecture
2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems, 2015As new massively multithreaded many-core architectural designs continue to evolve, the challenge of finding schedules that exploit concurrency, reuse and locality remains. Classically, data transformations were made with a limited view of both the memory hierarchy and the parallelism available to the machine.
Sunil Shrestha +5 more
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Power Gating Clustered Many-Core Architectures
Journal of Low Power Electronics, 2008Many-core architectures provide a computation platform with high execution throughput, enabling them to efficiently execute workloads with a significant degree of thread-level parallelism, like networking, DSP and e-commerce. The burst-like nature of these workloads implies that most of the time several cores are idle; therefore, there is a large ...
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Visualizing complex dynamics in many-core accelerator architectures
2010 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS), 2010While many-core accelerator architectures, such as today's Graphics Processing Units (GPUs), offer orders of magnitude more raw computing power than contemporary CPUs, their massive parallelism often produces complex dynamic behaviors even with the simplest applications.
Aaron Ariel +3 more
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Stochastic testing of processing cores in a many-core architecture
Integration, 2016Abstract A promising solution to reliability challenges in nano-scale fabrication technologies is self-test and reconfiguration. In this direction, we propose an autonomous test mechanism for online detection of permanent faults in many-core processors. Several hardware test components are incorporated in the many-core architecture.
Arezoo Kamran, Zainalabedin Navabi
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Accelerating Asian option pricing on many‐core architectures
Concurrency and Computation: Practice and Experience, 2015SummaryIn this paper, we start by looking at the algorithms and the numerical methods of pricing one exotic option, the strong path dependent Asian option using the Black–Scholes pricing model. We cover both geometric average and arithmetic average schemes that lead us to two different numerical solutions.
Shuo Li, James Lin
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Performance analysis of the OP2 framework on many-core architectures
ACM SIGMETRICS Performance Evaluation Review, 2011We present a performance analysis and benchmarking study of the OP2 "active" library, which provides an abstraction framework for the solution of parallel unstructured mesh applications. OP2 aims to decouple the scientific specification of the application from its parallel implementation, achieving code longevity and near-optimal performance through re-
Mike B. Giles +4 more
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Larrabee: A Many-Core Intel Architecture for Visual Computing
2010This talk will describe a many-core visual computing architecture code named Larrabee. Larrabee uses multiple in-order x86 CPU cores that are augmented by a wide vector processor unit, as well as some fixed function logic blocks. The talk will go into an overview of the Larrabee architecture and will cover the LRB Vector ISA in detail. We'll then cover
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Many-core System-on-Chip: architectures and applications
Microprocessors and Microsystems, 2016Mohamed Bakhouya +3 more
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