Results 31 to 40 of about 381,026 (309)
MEDEA: A Hybrid Shared-memory/Message-passing Multiprocessor NoC-based Architecture [PDF]
, 2010 The shared-memory model has been adopted, both for data exchange as well as synchronization using semaphores in almost every on-chip multiprocessor implementation, ranging from general purpose chip multiprocessors (CMPs) to domain specific multi-core ...
Ruo Roch, Massimo +10 more
core +1 more source
BMC Bioinformatics, 2019 Background Tandem mass spectrometry (MS/MS)-based database searching is a widely acknowledged and widely used method for peptide identification in shotgun proteomics. However, due to the rapid growth of spectra data produced by advanced mass spectrometry
Chuang Li, Kenli Li, Keqin Li, Feng Lin
doaj +1 more source
Exploiting memory allocations in clusterised many‐core architectures [PDF]
IET Computers & Digital Techniques, 2019 Power‐efficient architectures have become the most important feature required for future embedded systems. Modern designs, like those released on mobile devices, reveal that clusterisation is the way to improve energy efficiency. However, such architectures are still limited by the memory subsystem (i.e. memory latency problems). This work investigates
Garibotti, Rafael +5 more
openaire +1 more source
Signaling Load Reduction in 5G Network and Beyond [PDF]
Engineering and Technology Journal, 2021 A huge traffic flow in the next generation network is anticipated due to the rising in number of users and the new services that need low end-to-end latency causing a large signaling load on the Core Network (CN).
Mohammed Waheed, Azzad Saeed, Thanaa Abd
doaj +1 more source
Carrie-ou/PowerModelingforPhytiumFT-2000-64Multi-core-Architecture: Measurement_Data_v1.2
, 2020 This is the measurement data used in Power Modeling for Phytium FT-2000+/64 Multi-core ...
Carrie-ou
core +1 more source
P-Socrates: Parallel Software Framework for Time-Critical many-core Systems [PDF]
, 2017 Poster presented in 12th Conference on High Performance and Embedded Architecture and Compilation (HIPEAC 2017), EU Projects Poster Session. Stockholm, Sweden.SOLUTION FOR SCALING PERFORMANCE IN EMBEDED APPLICATIONS: process big amounts of data from ...
Pinho, Luís Miguel, P-SOCRATES Project
core +1 more source
A small and power efficient checkpoint core architecture for manycore processors [PDF]
, 2015 This article describes and evaluates a small, out-of-order, simultaneous multithreaded (SMT) core architecture suitable for power constrained microprocessors, such as manycore microprocessors for high performance computing.
Akkary, Haitham H., Sharafeddin, Mageda
core +1 more source
Bioinformatics Performance Comparison of Many-core Tile64 vs. Multi-core Intel Xeon
CLEI Electronic Journal, 2014 The performance of the many-core Tile64 versus the multi-core Xeon x86 architecture on bioinformatics has been compared. We have used the pairwise algorithm MC64-NW/SW that we have previously developed to align nucleic acid (DNA and RNA) and peptide ...
Myriam Kurtz +6 more
doaj +1 more source
Multicore Photonic Complex-Valued Neural Network with Transformation Layer
Photonics, 2022 Photonic neural network chips have been widely studied because of their low power consumption, high speed and large bandwidth. Using amplitude and phase to encode, photonic chips can accelerate complex-valued neural network computations. In this article,
Ruiting Wang +7 more
doaj +1 more source
Microgrid - The microthreaded many-core architecture
CoRR, 2013 30 pages, 16 ...
openaire +2 more sources