Exploiting Ferroelectric and Spintronic Dynamics for Neural Network Computation
Ferroelectric and spintronic devices, relying on the control of polarization and magnetization, offer intrinsically fast, durable, energy‐efficient, and low‐latency building blocks for analog in‐memory computing. The hysteretic dynamics of an order parameter are leveraged to provide nonvolatile, multistate memory and nonlinear switching. Brain‐inspired
Dashiell Harrison +4 more
wiley +1 more source
Damage-free van der Waals metal/NbO<sub>x</sub>-NbSe<sub>2</sub> integration for reliable and flexible memristor in neuromorphic computing. [PDF]
Phan TL +10 more
europepmc +1 more source
Single‐Step Analog In‐Memory Matrix Computation in Three‐Dimensional Circuits
A wooden model illustrates a 3D memristive array designed for single‐step kernel convolutions. It shows how two‐dimensional input data are mapped into the 3D array and convolved in parallel with stored kernels. Color‐coded connection points represent programmed memory‐element values, with each color corresponding to a specific kernel weight.
Alireza Jaberi Rad +8 more
wiley +1 more source
Spiking without Resets: Continuous Integrate-and-Fire Dynamics in Neuronal Circuits. [PDF]
Fenollosa R, Bisquert J.
europepmc +1 more source
A two‐terminal IGZO memtransistor enabling low‐voltage operation is demonstrated through coupling enhancement. By utilizing drain‐induced Fowler–Nordheim tunneling, the device achieves programming below 10 V with a large memory window and high on/off ratio.
Junhyeong Park +5 more
wiley +1 more source
Photo-Induced Valence Changed Memristor Based on WO<sub>3</sub> and Polyvinyl Alcohol Nanocomposites for In-Sensor Reservoir Computing. [PDF]
Zhang J +8 more
europepmc +1 more source
Vertical NAND Flash Memory‐Based Bayesian Neural Networks With Intrinsic Gaussian Weight Sampling
Commercial vertical NAND flash memory supports Bayesian neural networks by using paired cells to produce bell‐shaped weight distributions. Read voltage controls their spread without additional memory cells or changes to the array structure. Simulations based on device measurements demonstrate improved uncertainty estimation and accuracy gains of up to ...
Sung‐Ho Park +8 more
wiley +1 more source
A 3D vertically integrated synaptic pillar with an n–p–n–p–n channel is proposed within a compact footprint for neuromorphic computing. By combining volatile 1T‐DRAM and non‐volatile SONOS tiers, the system mitigates refresh power overhead. Optimized by an adaptive dynamic pulse scheme, the device achieves high linearity and 87% MNIST classification ...
Eungi Hwang +3 more
wiley +1 more source
Charge-Trapping-Enhanced Resistive Switching and Charge Storage in Silk Fibroin-TiO<sub>2</sub> Composite Memristors. [PDF]
Song S +6 more
europepmc +1 more source

