Results 261 to 270 of about 31,656 (310)

Itanium processor microarchitecture

IEEE Micro, 2000
The Itanium processor is the first implementation of the IA-64 instruction set architecture (ISA). The design team optimized the processor to meet a wide range of requirements: high performance on Internet servers and workstations, support for 64-bit addressing, reliability for mission-critical applications, full IA-32 instruction set compatibility in ...
Harsh Sharangpani, Ken Arora
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Verification of processor microarchitectures

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146), 2003
This paper develops a new abstraction technique for processor microarchitecture validation. An abstract finite-state machine model is derived directly from the processor HDL description. This model, along with information about the instruction set, is used for validation coverage analysis.
Jian Shen, Jacob A. Abraham
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Integrated microarchitectures

IEEE Micro, 2005
Trends in CMOS technology point to an era of high-performance microprocessor design in which problems such as power consumption and cooling, deviceand chip-level variability, and hard and soft errors threaten to slow down historically established performance growth rates.
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POWER4 system microarchitecture

IBM Journal of Research and Development, 2002
The IBM POWER4 is a new microprocessor organized in a system structure that includes new technology to form systems. The name POWER4 as used in this context refers not only to a chip, but also to the structure used to interconnect chips to form systems.
Joel M. Tendler, J. Steve Dodson, J. S. Fields Jr., Hung Q. Le, Balaram Sinharoy   +4 more
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Microarchitecture description techniques

ACM SIGMICRO Newsletter, 1982
A procedure is outlined for describing the microarchitecture of a horizontal processor such that a retargetable Microprogram Compiler System can incorporate the description to generate microcode for that processor. The microarchitecture description methodology is an organized approach to defining a machine's microinstruction formats, fields, and ...
John L. Gieser, Robert J. Sheraga
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POWER5 system microarchitecture

IBM Journal of Research and Development, 2005
This paper describes the implementation of the IBM POWER5TM chip, a two-way simultaneous multithreaded dual-core chip, and systems based on it. With a key goal of maintaining both binary and structural compatibility with POWER4TM systems, the POWER5 microprocessor allows system scalability to 64 physical processors.
Balaram Sinharoy, Ronald N. Kalla, Joel M. Tendler, Richard J. Eickemeyer, Jody B. Joyner   +4 more
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Tuning adaptive microarchitectures

International Journal of Embedded Systems, 2006
Microprocessors are designed with a fixed set of microarchitectural resources. However, resource requirements vary across programs and within a program as it passes through different phases of execution. This mismatch between the microarchitecture and program requirements leads to sub-optimal power/performance.
Ashutosh S. Dhodapkar, James E. Smith 0001   +1 more
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Designing robust microarchitectures

Proceedings of the 41st annual Design Automation Conference, 2004
A fault-tolerant approach to microprocessor design, developed at the University of Michigan, is presented. Our approach is based on the use of in-situ checker components that validate the functional and electrical characteristics of complex microprocessor designs. Two design techniques are highlighted: a low-cost double-sampling latch design capable of
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Microarchitecture of HaL's CPU

Digest of Papers. COMPCON'95. Technologies for the Information Superhighway, 2002
The HaL PM1 CPU is the first implementation of the 64-bit SPARC Version 9 instruction set architecture. The processor utilizes superscalar instruction issue, register renaming, and a dataflow model of execution. Instructions can complete out-of-order and are later committed in order. The PM1 CPU maintains precise state. The processor has a higher level
Niteen Patkar, Akira Katsuno, Simon Li, Tak Maruyama, Sunil Savkar, Mike Simone, Gene Shen, Ravi Swami, DeForest Tovey   +8 more
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Framboid Microarchitecture

2021
Framboids can be classified in terms of whether their constituent microcrystals are regularly arranged (ordered in a single domain), randomly arranged (disordered), or mixtures of both (partially ordered or multiple domains). The relative proportions of these three types are unknown, but there may be a tendency for the proportion of ordered framboids ...
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