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Interference resilient PDES on multi-core systems

Proceedings of the 1st ACM SIGSIM Conference on Principles of Advanced Discrete Simulation, 2013
Parallel Discrete Event Simulation (PDES) harnesses the power of parallel processing to improve the performance and capacity of simulation, supporting bigger models, in more details and for more scenarios. PDES engines are typically designed and evaluated assuming a homogeneous parallel computing system that is dedicated to the simulation application ...
Jingjing Wang   +2 more
openaire   +1 more source

Testing Performance-Isolation in Multi-core Systems

2019 IEEE 43rd Annual Computer Software and Applications Conference (COMPSAC), 2019
In this paper we present a methodology to be used for quantifying the level of performance isolation for a multi-core system. We have devised a test that can be applied to breaches of isolation in different computing resources that may be shared between different cores.
Jakob Danielsson   +4 more
openaire   +1 more source

Effective Evaluation of Multi-core Based Systems

2013 IEEE 12th International Symposium on Parallel and Distributed Computing, 2013
This work proposes a practical technique to reduce the evaluation cost of multi-core based systems, when these systems are evaluated with parallel benchmarks. The proposed technique highlights the amount of redundancy in a set of parallel benchmarks and reduces this set to a subset of benchmarks such that: (i) the selected benchmarks are representative
Rosario Cammarota   +3 more
openaire   +1 more source

An embedded multi-core biometric identification system

Microprocessors and Microsystems, 2011
Biometric identification systems exploit automated methods of recognition based on physiological or behavioural characteristics. Among these, fingerprints are very reliable as biometric identifiers. In order to build embedded systems performing real-time authentication, a fast computational unit for image processing is required.
G. Danese   +3 more
openaire   +1 more source

Reinventing Lock Modeling for Multi-Core Systems

2010 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, 2010
Multi-core architectures have become mainstream. Trends suggest that the number of cores integrated on a single chip will continue to increase. However, lock contention in applications or kernels can degrade the scalability so significantly that the speedup decreases with the increasing number of cores (thrashing). Although the phenomenon can be easily
Yan Cui   +5 more
openaire   +1 more source

Multi-core based HEVC hardware decoding system

2014 IEEE International Conference on Multimedia and Expo Workshops (ICMEW), 2014
In this demo, a scalable HEVC hardware decoder is demonstrated for various applications including UHD. The architecture includes a control logic for multi-core management and flexible in-loop filters that can process boundaries of picture partitions without a separate in-loop filter unit from the pipeline.
null Hyunmi Kim   +3 more
openaire   +1 more source

Predictive Energy Management on Multi-core Systems

2017
To meet climate agreements, electric vehicles will become very important in the next few years. One class of electric vehicles are Fully Electric Vehicles (FEVs) which are purely powered by electric energy. At the moment the driving range of FEVs is very limited compared to vehicles driven by internal combustion engines. To contribute to increasing the
Stephanie Grubmüller   +5 more
openaire   +1 more source

Efficient Process Scheduling for Multi-core Systems

2022 IEEE 8th Intl Conference on Big Data Security on Cloud (BigDataSecurity), IEEE Intl Conference on High Performance and Smart Computing, (HPSC) and IEEE Intl Conference on Intelligent Data and Security (IDS), 2022
Xiangyu Gao, Meikang Qiu
openaire   +1 more source

Task Parallel Scheduling over Multi-core System

2009
Parallel scheduling research based on multi-core system become more and more popular due to its super computing capacity. Scheduling fairness and load balance is the key performance indicator for current scheduling algorithm. The action of scheduler can be modeled as this: accepting the task state graph, task scheduling analyzing and putting the ...
openaire   +1 more source

A Survey of Timing Verification Techniques for Multi-Core Real-Time Systems

ACM Computing Surveys, 2020
Claire Maiza   +2 more
exaly  

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