Results 121 to 130 of about 3,527 (181)

Genetic Reduction of the Translational Repressors FMRP and 4E-BP2 Preserves Memory in Mouse Models of Alzheimer's Disease. [PDF]

open access: yesAging Cell
Ribeiro FC   +11 more
europepmc   +1 more source

Elevated mevalonolactone from Ruminococcus torques contributes to metabolically unhealthy obesity development. [PDF]

open access: yesJ Biol Chem
Nie HY   +13 more
europepmc   +1 more source
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Design of MVL Operands

IETE Journal of Research, 1990
A ternary logic operand implementation scheme in 3-μ CMOS technology is presented. Both unary and multiple input operands are designed by cascading threshold detectors with pass-transistors. The circuits have negligible dc dissipation and occupy a small chip area. This scheme is extendable as given any ternary logic operand, its circuit can be obtained.
Hitesh Ahuja
exaly   +2 more sources

RCM-MVI: a recursive consensus MVL minimization algorithm

Proceedings of the Twentieth International Symposium on Multiple-Valued Logic, 2002
A heuristic minimization algorithm based on the recursive application of the familiar consensus operation is presented. Unlike traditional consensus-based algorithms, it allows for the early detection of essential and pseudoessential prime implicants. This means that a solution is usually determined without all prime implicants being generated.
Gerhard W. Dueck, D. Michael Miller
openaire   +2 more sources

Arithmetic Algorithms and Circuits to Convert MVL to MVL Coded Decimal and Vice Versa

2008 3rd International Conference on Information and Communication Technologies: From Theory to Applications, 2008
The purpose of this paper is to present new algorithms and circuits to convert from MVL (Multiple Valued Logic) to MVL Coded Decimal (MVL-CD) and vice versa. We will introduce two conversion techniques: the first one is called "Addition-Subtraction technique" (AST) while the other method is called "Division-Multiplication Technique" (DMT). Based on AST,
Hassan Amine Osseily, Ali Massoud Haidar
openaire   +1 more source

Expandable MVL Inverter Compatible with Standard CMOS Process and Its Application to MVL Hysteresis Comparator

2013 IEEE 43rd International Symposium on Multiple-Valued Logic, 2013
In this paper, a novel voltage-mode MVL inverter is proposed. The proposed inverter consists of two circuit blocks: MVL threshold comparator and Multi-level generator, which can be implemented by standard CMOS technologies. Next, the inverted MVL hysteresis comparator is also proposed as the application of the proposed MVL inverter.
Arif Abdul Mannan   +4 more
openaire   +2 more sources

Design and implementation of MVL

ACM SIGGRAPH 2005 Posters on - SIGGRAPH '05, 2005
Developing medical VR simulators takes much labor and cost because of its complexity and high requirements for simulation. In this paper, we propose MVL, which gives simulation modules of several significant medical manipulations considering multiple organ interaction.
Yoshihiro Kuroda   +4 more
openaire   +2 more sources

Generic implementation of DD packages in MVL

Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium, 1999
This paper presents a generic approach to implementation of Decision Diagrams (DDs) for representation and manipulation of Multi-Valued Logic (MVL) functions. The core package is based on recursive synthesis operations, where the recursive step is given by a table look-up technique.
Rolf Drechsler   +2 more
openaire   +2 more sources

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