Results 151 to 160 of about 4,682 (213)

Elevated mevalonolactone from Ruminococcus torques contributes to metabolically unhealthy obesity development. [PDF]

J Biol Chem
Nie HY, Zhao MF, Wu TY, Zou MJ, Tang YP, Wang XC, Wang NN, Zhou ZY, Bi Y, Zhao Y, Sun XT, Zhang JZ, Fang L, Li CJ.   +13 more
europepmc   +1 more source

The Effects of Short-Term Post-Exposure to 3.6 GHz 5G Mobile Phone Electromagnetic Exposure on Static and Dynamic Postural Control in Healthy Adults: A Randomized Sham-Controlled Pilot Study. [PDF]

Sensors (Basel)
Torkan A, Zoghi M, Foroughimehr N, Jaberzadeh S.   +3 more
europepmc   +1 more source

Xylem anatomy and pit architecture but not perforation-plate types shape hydraulic strategies against hypersaline and drought stress in eight woody mangroves. [PDF]

Tree Physiol
Wei Y, Jiang X, Choat B, Aritsara ANA, Cao K, Chen Y.   +5 more
europepmc   +1 more source

A Universal Implementation Approach for Multivalued Logic Gates Based on Negative Transconductance in Series-Connected Two-Dimensional Transistors. [PDF]

ACS Nano
Zhao G, Wen W, Liao K, Coquet P, Wang X, Huang M, Tay BK.   +6 more
europepmc   +1 more source

Altered sensorimotor-association axis patterning of global functional connectivity in an autism subtype with low levels of language, intellectual, and adaptive functioning

Severino I, Mandelli V, Bertelsen N, Lombardo MV.   +3 more
europepmc   +1 more source

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Design of MVL Operands

IETE Journal of Research, 1990
A ternary logic operand implementation scheme in 3-μ CMOS technology is presented. Both unary and multiple input operands are designed by cascading threshold detectors with pass-transistors. The circuits have negligible dc dissipation and occupy a small chip area. This scheme is extendable as given any ternary logic operand, its circuit can be obtained.
Hitesh Ahuja, D Nagchoudhuri
exaly   +2 more sources

MVL‐PUFs: multiple‐valued logic physical unclonable functions

International Journal of Circuit Theory and Applications, 2016
SummaryPhysical unclonable functions (PUFs) are promising hardware security primitives suitable for protecting resource‐constrained devices. In this paper, we propose to use multiple‐valued logic (MVL) for implementing hardware‐efficient PUF integrated circuits.
Sha Tao, Elena Dubrova
openaire   +2 more sources

Design of novel Multiple Valued Logic (MVL) circuits

2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2), 2017
Background: Multiple-Valued Logic (MVL) is the non-binary-valued system, in which more than two levels of information content are available, i.e., L>2. In modern technologies, the dual level binary logic circuits have normally been used. However, these suffer from several significant issues such as the interconnection considerations including the ...
V S Kanchana Bhaaskaran
exaly   +2 more sources

Weighted and Ordered Direct Cover Algorithms for Minimization of MVL Functions

Multiple-Valued Logic (ISMVL), Proceedings of the International Symposium on, 2007
In this paper, weighted and ordered direct cover algorithms (abbreviated as WDC and ODC, respectively) for synthesis of multiple-valued logic (MVL) functions are proposed. The algorithms are tested using 50000 randomly generated 2-variable 4-valued and 2-variable 5-valued functions.
Mostafa Abd-El-Barr
exaly   +3 more sources

An analysis of MVL neural operators using feed forward backpropagation: Realization and application of logic synthesis

, 2015
© 2015 IEEE. In this paper, a Neural Network Deployment (NND) algorithm is presented to realize and synthesize Multi-Valued Logic (MVL) functions. The algorithm is combined with back-propagation learning capability and MVL operators.
Ashutosh Kumar Singh, Lenin Gopal, Adib Kabir Chowdhury   +2 more
exaly   +3 more sources