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Technique of computing logic derivatives for MVL-functions
Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96), 2002A technique to compute logic derivatives of MVL-functions is considered based on four algorithms, two of them are new. At first these are symbolic and matrix algorithms to find logic derivatives with respect to variables, and, secondly, partial direct and inverse derivatives.
Vlad P. Shmerko +3 more
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Descending Order Transformation-based Synthesis of MVL Reversible Circuits
2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL), 2021Transformation-based synthesis is a straightforward technique for determining a circuit for a reversible function. Various methods employing the transformation-based approach have been previously proposed. For an r-valued function, the existing methods consider the function specification in ascending order from the input assignment 0,0,…,0 to the input
D. Michael Miller, Gerhard W. Dueck
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From a fuzzy flip-flop to a MVL flip-flop
Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329), 2003The paper presents a circuit description of a MVL flip-flop which is implemented in MOS technology. The circuit has its origins in a bipolar implementation of a fuzzy flip-flop. The proposed circuit not only simplifies the original bipolar design but it offers considerable potential for a VLSI implementation.
Liam P. Maguire +2 more
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Spectral transforms of mixed-radix MVL functions
33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings., 2004Mixed-radix "Multiple Valued Logic" (MVL) functions are assumed to be finite and discrete-valued and depend on a finite-valued variable support set {x/sub i/,...,x/sub j/} such that x/sub i/ is q/sub i/-valued and x/sub j/ is q/sub j/-valued with q/sub i/ /spl ne/ q/sub j/.
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The evaluation of full sensitivity for test generation in MVL circuits
Proceedings 25th International Symposium on Multiple-Valued Logic, 2002The evaluation of a method for test generation for MVL circuits, based on the notion of full sensitivity, is given. The estimation is made on the functional level, by establishing a lower bound on the number of m-valued n-variable functions that are fully sensitive to all their variables.
Elena Dubrova +2 more
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Direct cover MVL minimization with cost-tables
[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic, 2003A direct cover algorithm for minimizing multivalued logic functions is described. The use of cost tables facilitates cost efficient implementations. Current-mode CMOS circuits are considered as target implementations. However, the algorithm can be readily adapted to different technologies by making appropriate changes in the cost tables.
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Layered MVL neural networks capable of recognizing translated characters
[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic, 2003The multivalued logic (MVL) neurons constituting the layered MVL neural network use MVL operations to produce analog responses to be fed to the respective quantizers. A four-layered MVL neural network model capable of recognizing translated characters is presented.
Tatsuki Watanabe, Masayuki Matsumoto
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On the synthesis of MVL functions for current-mode CMOS circuits implementation
[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic, 2003Four-valued, one-variable multivalued logic (MVL) functions are synthesized using current-mode CMOS logic (CMCL) circuits. Use is made of the fact that in CMCL, addition of logic values (represented using discrete current values) can be performed at no cost and that negative logic values are readily available by reversing the direction of current flow.
Mostafa I. H. Abd-El-Barr, M. I. Mahroos
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On the synthesis of MVL functions using input and output phase assignments
Proceedings 1997 27th International Symposium on Multiple- Valued Logic, 2002In this paper, a number of decomposition based mapping techniques are proposed. In these techniques, the synthesis problem is formulated as a mapping from an input matrix to an output matrix. The minimization is obtained by constructing a matching-count matrix.
Mostafa I. H. Abd-El-Barr +2 more
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Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL
37th International Symposium on Multiple-Valued Logic (ISMVL'07), 2007Designing modern circuits comprised of millions of gates is a very challenging task. Therefore new directions are investigated for efficient modeling and verification of such systems. Recently, a new language, SystemVerilog, was introduced and became an IEEE standard.
Mahsan Amoui +3 more
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