Results 141 to 150 of about 3,362 (182)

Direct cover MVL minimization with cost-tables

[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic, 2003
A direct cover algorithm for minimizing multivalued logic functions is described. The use of cost tables facilitates cost efficient implementations. Current-mode CMOS circuits are considered as target implementations. However, the algorithm can be readily adapted to different technologies by making appropriate changes in the cost tables.
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The evaluation of full sensitivity for test generation in MVL circuits

Proceedings 25th International Symposium on Multiple-Valued Logic, 2002
The evaluation of a method for test generation for MVL circuits, based on the notion of full sensitivity, is given. The estimation is made on the functional level, by establishing a lower bound on the number of m-valued n-variable functions that are fully sensitive to all their variables.
Elena Dubrova, Dilian Gurov, Jon C. Muzio   +2 more
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From a fuzzy flip-flop to a MVL flip-flop

Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329), 2003
The paper presents a circuit description of a MVL flip-flop which is implemented in MOS technology. The circuit has its origins in a bipolar implementation of a fuzzy flip-flop. The proposed circuit not only simplifies the original bipolar design but it offers considerable potential for a VLSI implementation.
Liam P. Maguire, T. Martin McGinnity, L. J. McDaid   +2 more
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Spectral transforms of mixed-radix MVL functions

33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings., 2004
Mixed-radix "Multiple Valued Logic" (MVL) functions are assumed to be finite and discrete-valued and depend on a finite-valued variable support set {x/sub i/,...,x/sub j/} such that x/sub i/ is q/sub i/-valued and x/sub j/ is q/sub j/-valued with q/sub i/ /spl ne/ q/sub j/.
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Layered MVL neural networks capable of recognizing translated characters

[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic, 2003
The multivalued logic (MVL) neurons constituting the layered MVL neural network use MVL operations to produce analog responses to be fed to the respective quantizers. A four-layered MVL neural network model capable of recognizing translated characters is presented.
Tatsuki Watanabe, Masayuki Matsumoto
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On the synthesis of MVL functions for current-mode CMOS circuits implementation

[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic, 2003
Four-valued, one-variable multivalued logic (MVL) functions are synthesized using current-mode CMOS logic (CMCL) circuits. Use is made of the fact that in CMCL, addition of logic values (represented using discrete current values) can be performed at no cost and that negative logic values are readily available by reversing the direction of current flow.
Mostafa I. H. Abd-El-Barr, M. I. Mahroos
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On the synthesis of MVL functions using input and output phase assignments

Proceedings 1997 27th International Symposium on Multiple- Valued Logic, 2002
In this paper, a number of decomposition based mapping techniques are proposed. In these techniques, the synthesis problem is formulated as a mapping from an input matrix to an output matrix. The minimization is obtained by constructing a matching-count matrix.
Mostafa I. H. Abd-El-Barr, Muhammad Nayyar Hasan, G. A. Hamid   +2 more
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Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL

37th International Symposium on Multiple-Valued Logic (ISMVL'07), 2007
Designing modern circuits comprised of millions of gates is a very challenging task. Therefore new directions are investigated for efficient modeling and verification of such systems. Recently, a new language, SystemVerilog, was introduced and became an IEEE standard.
Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler   +3 more
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MVL‐PUFs: multiple‐valued logic physical unclonable functions

International Journal of Circuit Theory and Applications, 2016
SummaryPhysical unclonable functions (PUFs) are promising hardware security primitives suitable for protecting resource‐constrained devices. In this paper, we propose to use multiple‐valued logic (MVL) for implementing hardware‐efficient PUF integrated circuits.
Sha Tao, Elena Dubrova
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A new structure for CMOS realization of MVL functions

International Journal of Electronics, 1993
A new structure is proposed for the realization of multiple-valued logic (MVL) functions. Multiple-valued logic levels are represented in terms of current values, which represent the inputs and the outputs of the MVL circuits. Binary voltage signals are generated inside the structure by using a circuit element called threshold.
A. K. JAIN, M. H. ABD-EL-BARR, R. J. BOLTON   +2 more
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