Results 161 to 170 of about 4,699 (212)

Genetic Reduction of the Translational Repressors FMRP and 4E-BP2 Preserves Memory in Mouse Models of Alzheimer's Disease. [PDF]

open access: yesAging Cell
Ribeiro FC   +11 more
europepmc   +1 more source

Elevated mevalonolactone from Ruminococcus torques contributes to metabolically unhealthy obesity development. [PDF]

open access: yesJ Biol Chem
Nie HY   +13 more
europepmc   +1 more source

Synthesis of MVL Functions - Part I: The Genetic Algorithm Approach [PDF]

open access: yes, 2006
Multiple-Valued Logic (MVL) has been used in the design of a number of logic systems, including memory, multi-level data communication coding, and a number of special purpose digital processors. Several algorithms have been proposed in the literature for
Mostafa Abd-El-Barr
exaly   +2 more sources
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RCM-MVI: a recursive consensus MVL minimization algorithm

Proceedings of the Twentieth International Symposium on Multiple-Valued Logic, 2002
A heuristic minimization algorithm based on the recursive application of the familiar consensus operation is presented. Unlike traditional consensus-based algorithms, it allows for the early detection of essential and pseudoessential prime implicants. This means that a solution is usually determined without all prime implicants being generated.
Gerhard W. Dueck, D. Michael Miller
openaire   +2 more sources

Arithmetic Algorithms and Circuits to Convert MVL to MVL Coded Decimal and Vice Versa

2008 3rd International Conference on Information and Communication Technologies: From Theory to Applications, 2008
The purpose of this paper is to present new algorithms and circuits to convert from MVL (Multiple Valued Logic) to MVL Coded Decimal (MVL-CD) and vice versa. We will introduce two conversion techniques: the first one is called "Addition-Subtraction technique" (AST) while the other method is called "Division-Multiplication Technique" (DMT). Based on AST,
Hassan Amine Osseily, Ali Massoud Haidar
openaire   +1 more source

Expandable MVL Inverter Compatible with Standard CMOS Process and Its Application to MVL Hysteresis Comparator

2013 IEEE 43rd International Symposium on Multiple-Valued Logic, 2013
In this paper, a novel voltage-mode MVL inverter is proposed. The proposed inverter consists of two circuit blocks: MVL threshold comparator and Multi-level generator, which can be implemented by standard CMOS technologies. Next, the inverted MVL hysteresis comparator is also proposed as the application of the proposed MVL inverter.
Arif Abdul Mannan   +4 more
openaire   +2 more sources

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